DCVS-Aware Interprocessor Communication Buffering
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Solution Overview
Problem
Portable computing devices (PCDs) face increased power consumption due to sudden increases in clock frequency caused by random messages or interrupts, which contradicts the purpose of Dynamic Clock and Voltage Scaling (DCVS) algorithms, particularly in multi-core processors where interprocessor communications can lead to unnecessary power consumption.
Innovation Solution
Implementing a system that allows for DCVS-aware interprocessor communications by determining whether to send data packets to a processing component or a buffer based on the workload information of the receiving processing component, thereby avoiding unnecessary increases in power consumption by deferring data transmission when the receiving component is busy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If DCVS algorithm is implemented to reduce power consumption, then power consumption is reduced, but sudden increases in clock frequency occur when receiving random messages/interrupts
Solution Approach 1:
The sending processor checks the workload status of the receiving processor before transmitting data packets. This preliminary action allows the system to anticipate potential frequency increases and avoid transmitting packets that would trigger unnecessary DCVS frequency adjustments, thereby maintaining power savings while ensuring reliable data transmission when needed.
2Productivity
If multiple messages/interrupts are received at random times, then CPU load increases, but power consumption increases significantly due to frequency scaling
Solution Approach 1:
The system implements feedback by having the sending processor query the workload status of the receiving processor before transmitting data. This feedback mechanism allows the sending processor to adjust its transmission behavior based on the receiving processor's current load, avoiding unnecessary frequency increases and power consumption while still maintaining productivity through selective packet transmission.
3Ease of operation
If data packets are sent continuously to maintain communication, then data transmission is maintained, but unnecessary power consumption occurs during high workload periods
Solution Approach 1:
The system dynamically adjusts data transmission based on the workload status of the receiving processor. When the receiving processor is in a low workload state, data packets are transmitted to maintain communication continuity. When the receiving processor is in a high workload state, transmission is deferred or buffered, reducing power consumption while maintaining the ability to resume communication when needed.
Data Source
AI summary
Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic.