DCVS Latch Clock Gating for Wide Common-Mode Input Range
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Solution Overview
Problem
Differential cascode voltage switch (DCVS) latches face issues due to wide variations in common-mode input voltages, affecting their size, power consumption, and performance, as they need to operate reliably across a wide range of common-mode input voltages.
Innovation Solution
The latch device incorporates a differential pair, a differential circuit, and a clock gate circuit with reference-independent and reference-dependent circuits, which adjust the effective conductive widths based on the voltage levels of the input signals to maintain operation across a wide common-mode range, along with offset cancellation circuitry to mitigate voltage-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the latch device operates over a wide range of common-mode input voltages, then the adaptability is improved, but the headroom voltage variation causes issues with size, power consumption and performance
Solution Approach 1:
The patent implements dynamic adjustment of the headroom voltage by using a bias circuit that modifies the gate-source voltage of the differential pair transistors based on the common-mode input voltage level. This dynamic adaptation allows the latch to maintain consistent performance across a wide common-mode voltage range by automatically adjusting internal voltages to compensate for headroom variations.
Solution Approach 2:
The patent changes the operating parameters of the latch device by introducing a bias circuit that adjusts the gate-source voltage (Vgs) of the differential pair transistors. By varying this parameter in response to common-mode input voltage changes, the circuit maintains optimal operation across different voltage conditions, resolving the performance consistency issue while preserving wide adaptability.
2Reliability
If the headroom voltage is increased to maintain performance at high common-mode voltages, then the performance is improved, but the power consumption increases
Solution Approach 1:
The bias circuit dynamically adjusts the gate-source voltage parameter based on the common-mode input voltage level. At high common-mode voltages, it increases the headroom voltage to maintain performance, while at lower voltages, it reduces the headroom voltage to minimize power consumption. This parameter adaptation resolves the contradiction between performance and power consumption.
Solution Approach 2:
The circuit transitions from a static headroom voltage design to a dynamic one where the bias circuit continuously adjusts the gate-source voltage in response to common-mode voltage changes. This dynamic behavior allows the latch to optimize performance at high voltages while conserving power at lower voltages, eliminating the need for a consistently high power consumption design.
3Use of energy by moving object
If the headroom voltage is decreased to reduce power consumption, then the power consumption is reduced, but the performance degrades at high common-mode voltages
Solution Approach 1:
The bias circuit implements parameter change by adjusting the gate-source voltage of the differential pair transistors in response to common-mode input voltage levels. When high common-mode voltages are detected, the circuit increases the headroom voltage to maintain performance, preventing degradation while still allowing for low power consumption at lower voltage conditions.
Solution Approach 2:
The static headroom voltage is replaced with a dynamic adjustment mechanism that responds to common-mode voltage changes. This allows the circuit to maintain low power consumption during normal operation while automatically increasing performance capability when high common-mode voltages occur, resolving the contradiction between power efficiency and high-voltage performance.
Data Source
AI summary
A latch device includes a differential pair, a differential circuit, and a clock gate circuit. The differential pair receives differential input signals, and the differential circuit performs a logic operation on the differential input signals. The clock gate circuit is configured to supply a supply voltage from the power supply node to the first connection node according to a clock signal. The clock gate circuit includes a reference-independent circuit and a reference-dependent circuit. The reference-independent circuit is configured to control a first electrical path between the power supply node and the first connection node according to the clock signal. The reference-dependent circuit is configured to control a second electrical path between the power supply node and the first connection node according to the clock signal and a first control signal, wherein the first control signal is determined according to a voltage level of one of the differential input signals.