Dynamic Clock Voltage Scaling via Program Phase Detection
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Solution Overview
Problem
Existing dynamic clock and voltage scaling techniques in processors fail to account for significant variations in program runtime characteristics, particularly during memory-intensive phases, leading to missed opportunities for power and energy savings due to coarse time granularity and limited visibility into hardware behavior.
Innovation Solution
A cooperative hardware and software/firmware mechanism that detects program phases where the processor is waiting on data from the memory subsystem, using hardware counters to track statistics and predict memory-boundedness, allowing for fine-grained dynamic clock and voltage scaling to optimize power consumption and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If operating system software makes DCVS decisions based on coarse time granularity sampling, then device complexity is reduced, but power and energy saving opportunities are lost due to inability to detect fine-grained memory-bound phases
Solution Approach 1:
The patent segments the DCVS control mechanism into two independent components: (1) hardware performance monitoring units that continuously track processor activity at fine-grained levels, and (2) software DCVS controllers that make scaling decisions. This segmentation allows the hardware to capture detailed memory-bound phase information without increasing software complexity, enabling energy savings while maintaining manageable device complexity.
Solution Approach 2:
The patent introduces hardware performance monitoring units as an intermediary between the processor and the DCVS software. These units continuously monitor processor activity, detect memory-bound phases, and provide this information to the DCVS controller. This intermediary layer enables fine-grained detection capabilities without requiring the software to implement complex monitoring logic, thus achieving energy savings while keeping device complexity manageable.
2Loss of energy
If voltage and frequency are scaled down during memory-bound phases, then power consumption is reduced, but performance may be compromised if scaling occurs during compute-intensive phases
Solution Approach 1:
The patent implements a feedback mechanism where hardware performance monitoring units continuously track processor activity characteristics and provide this information to the DCVS controller. The controller uses this feedback to accurately identify memory-bound phases versus compute-intensive phases, enabling it to scale voltage and frequency down during memory-bound phases to reduce power consumption while maintaining full performance during compute-intensive phases.
Solution Approach 2:
The patent makes the DCVS system dynamic by enabling real-time adjustment of voltage and frequency based on detected program phases. The system transitions between different operating states (high performance vs. low power) depending on whether the processor is in a compute-intensive or memory-bound phase, optimizing the balance between power consumption and performance based on actual runtime conditions.
3Measurement precision
If hardware counters and cooperative mechanisms are added to detect program phases, then measurement precision of processor state is improved, but device complexity increases
Solution Approach 1:
The patent segments the measurement function into dedicated hardware performance monitoring units that are separate from the main processor and DCVS control logic. These specialized hardware counters focus exclusively on tracking processor activity characteristics, providing high measurement precision without requiring the main processor or DCVS software to become more complex. The segmentation isolates the complexity to dedicated monitoring components.
Solution Approach 2:
The hardware performance monitoring units operate autonomously, continuously tracking processor activity and automatically detecting memory-bound phases without requiring intervention from the main processor or software. This self-service capability enables high measurement precision while minimizing the complexity burden on the rest of the system, as the monitoring function is self-contained in dedicated hardware.
Data Source
AI summary
The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.