Deeply Depleted Channel CMOS for Low-Voltage Threshold Control
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing power consumption of bulk CMOS transistors as the operating voltage cannot be reduced further due to random dopant fluctuations, leading to increased power consumption and heat generation, making it difficult to adhere to Moore's Law and maintain the scalability of electronic devices.
Innovation Solution
The implementation of a Deeply Depleted Channel (DDC) design in Field Effect Transistors (FETs) with a deeply depleted region extending below the gate, allowing for precise control of threshold voltage and dynamic power management, which reduces power consumption and heat dissipation while maintaining compatibility with existing bulk CMOS processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of bulk CMOS transistor is decreased to increase transistor density, then the number of transistors per area increases, but the power consumption per transistor increases due to random dopant fluctuations
Solution Approach 1:
The patent changes the fundamental parameter of channel doping from conventional uniform doping to a graded doping profile where dopant concentration varies continuously from the source/drain regions toward the center of the channel. This parameter change allows precise control of threshold voltage and carrier concentration, enabling low-power operation at scaled dimensions by optimizing the balance between leakage current and drive current
Solution Approach 2:
The patent applies local quality by creating non-uniform dopant distribution within the channel, with different dopant concentrations at different locations. The dopant concentration is highest near source/drain and decreases toward the channel center, allowing local optimization of electrical properties to reduce power consumption while maintaining transistor density
2Use of energy by moving object
If the operating voltage is reduced to decrease power consumption, then the power consumption decreases, but the threshold voltage control becomes unstable due to random dopant fluctuations
Solution Approach 1:
The patent changes the doping parameter from uniform to graded distribution, which provides continuous control over the electric field and carrier concentration profile. This allows stable threshold voltage control at low operating voltages by optimizing the graded profile to compensate for random dopant fluctuations, enabling reliable low-power operation
Solution Approach 2:
The patent applies preliminary action by pre-configuring the graded dopant profile during manufacturing to anticipate and compensate for random dopant fluctuations. The optimized gradient is established beforehand to ensure stable threshold voltage control before the device operates, allowing reliable low-voltage operation
3Manufacturing precision
If the dopant concentration is increased to control threshold voltage, then the threshold voltage control improves, but the random dopant fluctuations increase leading to higher power consumption
Solution Approach 1:
The patent changes from uniform dopant concentration to a graded concentration profile, where the dopant amount is distributed optimally across the channel. This parameter change achieves precise threshold voltage control through the gradient effect rather than relying on high uniform concentration, thereby reducing random dopant fluctuations and power consumption
Data Source
AI summary
Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.