DDC Bus Level Shifter With Low Voltage Loss and Power Release
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Solution Overview
Problem
Conventional level shifters using 3.3V n-channel metal-oxide-semiconductor field-effect transistor (NMOS) pass gates result in significant voltage output reduction and costly logic errors when converting between DISPLAYPORT and HDMI interfaces, and they fail to release the display data channel when unpowered, leading to unnecessary power consumption.
Innovation Solution
A level shifter with a 3.3V thick oxide NMOS pass gate controlled by signals and a pull-up circuit, which reduces voltage threshold loss and allows for signal transmission without power when unpowered, using a 3.3V thick oxide NMOS pass gate and a pull-up circuit to adjust voltage levels between DISPLAYPORT and HDMI interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 3.3V NMOS pass gate is used to block 5V signals, then signal blocking is achieved, but voltage output is significantly reduced due to threshold voltage loss
Solution Approach 1:
The patent changes the gate voltage parameter from 3.3V to 5V, allowing the NMOS pass gate to block 5V signals while maintaining 5V output capability. This parameter change resolves the contradiction by eliminating threshold voltage loss that occurred with the 3.3V gate configuration.
Solution Approach 2:
The patent introduces dynamic control of the NMOS pass gate through a 5V control signal that can switch between blocking and passing states. This dynamic operation allows the gate to adaptively control signal flow while maintaining proper voltage levels, resolving the static voltage loss problem.
2Reliability
If the level shifter is always powered to maintain signal transmission capability, then signal transmission is ensured, but power consumption increases unnecessarily
Solution Approach 1:
The patent implements periodic or on-demand powering of the level shifter based on whether level shifting is actually required. The system can switch between powered and unpowered states, activating power only when signal transmission between different voltage domains is needed, thus reducing unnecessary power consumption while maintaining transmission capability when required.
3Use of energy by stationary object
If the level shifter is unpowered to reduce power consumption, then power saving is achieved, but the display data channel is not released
Solution Approach 1:
The patent extracts the channel release function from the powered level shifter operation. The NMOS pass gate is configured to automatically release the display data channel through its inherent electrical characteristics when unpowered, separating the channel release function from continuous power requirements and allowing the level shifter to remain unpowered while maintaining channel availability.
Data Source
AI summary
A system and method are disclosed for level shifting a DDC bus with a low voltage loss. A pull up circuit includes an NMOS transistor, a PMOS transistor and resistor. An NMOS pull up gate is also included in line with the DDC bus. When powered, the level shifter adjusts the voltage of transmitted signals to match the voltage of a receiving device. The resulting adjusted is slightly lower due to a threshold voltage lost across one or more transistors. Additionally, when unpowered, the level shifter releases the signal transmission line. Unadjusted signals can then be transmitted without consumption of power by the level shifter.