Deeply Depleted Channel Transistor Threshold Voltage Control
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing power consumption of bulk CMOS transistors as transistor size decreases, with increasing difficulty in accurately setting threshold voltage due to statistical variations in dopant concentration and placement, leading to increased leakage and power wastage, and the need for substantial changes in manufacturing processes to adopt new technologies.
Innovation Solution
The introduction of Deeply Depleted Channel (DDC) design for CMOS transistors allows for precise control of threshold voltage with a distinctive dopant profile notch, enabling tuning within a narrow range and separate control of body bias, allowing for low power consumption without requiring extensive changes in existing manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is decreased to increase transistor density, then transistor density is improved, but power consumption increases due to difficulty in controlling threshold voltage
Solution Approach 1:
The patent applies local quality by creating a notched dopant profile with a depletion region at a specific depth in the channel. This localized modification of dopant concentration at the threshold voltage setting depth enables precise control of threshold voltage in scaled transistors, allowing high transistor density while maintaining low power consumption through accurate VT control.
2Ease of manufacture
If conventional doping methods are used to set threshold voltage, then manufacturing process is simple, but threshold voltage control precision deteriorates due to statistical variations in dopant concentration
Solution Approach 1:
The patent segments the dopant profile into distinct regions: a lightly-doped channel region and a heavily-doped screening layer at a specific depth, with a notched depletion region in between. This segmentation allows the threshold voltage to be controlled by the screening layer dopant concentration, which can be precisely controlled through standard ion implantation processes, thereby improving VT control precision while maintaining manufacturing simplicity.
3Manufacturing precision
If dopant concentration is increased to control threshold voltage, then threshold voltage control is improved, but manufacturing complexity increases due to need for precise dopant placement
Solution Approach 1:
The patent performs preliminary action by forming the notched dopant profile and depletion region during the standard well formation process, before subsequent transistor fabrication steps. The screening layer is pre-doped at the threshold voltage setting depth, and the depletion region is created through selective dopant removal or prevention of dopant diffusion. This preliminary structuring enables accurate VT control without adding complexity to later manufacturing steps.
Data Source
AI summary
A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT (variation in VT) compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals of a gate electrode material so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low σVT) and VDD (the operating voltage supplied to the transistor), so that the body bias can be tuned separately from VT for a given device.