Double Diffused Drain MOS Device Gate-to-Drain Distance Optimization
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Solution Overview
Problem
Conventional MOS devices face challenges in downsizing while maintaining high operating voltage, as they require increased gate-to-drain distance to sustain high voltages, which hinders miniaturization.
Innovation Solution
A double diffused drain (DDD) MOS device structure is developed, featuring a diffused region with specific impurity types and patterned dielectric and conductive layers, allowing for reduced gate-to-drain distance without compromising high voltage sustainability through optimized impurity concentration and layer configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate-to-drain distance is increased to sustain high operating voltage, then the breakdown voltage is improved, but the device size increases and downsizing is hindered
Solution Approach 1:
The patent applies local quality by creating a double diffused drain structure where the drain region has non-uniform doping concentration - a lightly-doped first portion and a heavily-doped second portion. This local variation in impurity concentration allows the device to sustain high breakdown voltages while maintaining a compact gate-to-drain distance, as the specific local doping profile optimizes both voltage sustainability and spatial efficiency
Solution Approach 2:
The patent employs parameter changes by modifying the impurity concentration parameters within the drain region. By implementing a double diffused structure with different doping levels (lightly-doped first portion and heavily-doped second portion), the patent changes the electrical parameters to achieve high breakdown voltage without requiring increased gate-to-drain distance, thus resolving the contradiction between reliability and device dimensions
2Reliability
If the gate-to-drain distance is increased to sustain high operating voltage, then the breakdown voltage is improved, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the drain region into distinct portions - a first lightly-doped portion and a second heavily-doped portion. This segmented structure with patterned dielectric and conductive layers allows for optimized electrical performance and high breakdown voltage while maintaining manageable device complexity through systematic division of functional regions
Solution Approach 2:
The patent employs composite materials by combining multiple layers including patterned dielectric layers, conductive layers, and regions with different impurity concentrations. This composite structure integrates various materials and doping profiles to achieve high breakdown voltage performance while organizing complexity into a structured multi-layer architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The DDD MOS device achieves higher breakdown voltage with minimal increase in drain-to-source on-state resistance, enabling the design of power management ICs for higher voltage environments without the need for larger gate-to-drain distances.
Implementation Method 1
a diffused region including a first portion of a second impurity type and a second portion of a first impurity type in the substrate
Data Source
AI summary
A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion.