DDDMOS Conductive Layer Mitigates Band-to-Band Tunneling
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Solution Overview
Problem
Double diffused drain metal oxide semiconductor (DDDMOS) devices face limitations in breakdown voltage and band-to-band tunneling effects, restricting their application range and requiring additional costly manufacturing steps to integrate with low voltage devices.
Innovation Solution
A DDDMOS device with a conductive layer formed on a dielectric layer that overlaps part of the drift region between the gate and drain, modifying the electric field to reduce leakage current and increase breakdown voltage without additional process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional lithography and ion implantation processes are used to increase breakdown voltage and mitigate BTBT effect, then device performance is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
A conductive layer is introduced as an intermediary structure between the drain and the drift region. This conductive layer modifies the electric field distribution in the depletion region, effectively increasing breakdown voltage and mitigating BTBT effect without requiring additional lithography or ion implantation processes. The conductive layer acts as a mediator that achieves performance improvement through structural modification rather than additional manufacturing steps.
Solution Approach 2:
The invention changes the electrical parameters of the device by introducing a conductive layer with specific conductivity characteristics. This layer alters the electric field distribution and potential profile in the depletion region, thereby changing the breakdown characteristics and reducing BTBT effect. The parameter change is achieved through material selection and structural design rather than additional processing steps.
2Adaptability or versatility
If DDDMOS device is integrated with low voltage device in one substrate, then manufacturing flexibility is improved, but breakdown voltage decreases due to same ion implantation parameters
Solution Approach 1:
The conductive layer is selectively positioned in the high voltage DDDMOS device region to modify local electric field characteristics. This local modification allows the device to achieve higher breakdown voltage without affecting low voltage devices on the same substrate. The local quality change enables differentiated performance characteristics for different device types within the same integrated circuit.
Solution Approach 2:
The invention segments the substrate into regions with different device characteristics by selectively applying the conductive layer structure to high voltage devices while leaving low voltage devices unaffected. This segmentation allows independent optimization of breakdown voltage for high voltage devices without compromising the integration capability with low voltage devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively mitigates band-to-band tunneling effects and increases breakdown voltage, enabling broader application of DDDMOS devices while maintaining compatibility with common manufacturing processes for low voltage devices, thus enhancing operational reliability and reducing manufacturing costs.
Implementation Method 1
modifying the electric field to reduce leakage current and increase breakdown voltage
Implementation Method 2
the leakage current induced by the band-to-band tunneling (BTBT) effect will greatly increase
Implementation Method 3
a dielectric layer formed on both the gate and the second region
Data Source
AI summary
The present invention discloses a double diffused drain metal oxide semiconductor (DDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes: a drift region, a gate, a source, a drain, a dielectric layer, and a conductive layer. The drift region includes a first region and a second region. The gate is formed on the substrate, and overlaps the first region from top view. The source and drain are formed at both sides of the gate respectively, and the drain is located in the second region. The drain and the gate are separated by a portion of the second region from top view. The dielectric layer is formed by dielectric material on the gate and the second region. The conductive layer is formed by conductive material on the dielectric layer, and overlaps at least part of the second region from top view.