DDFS Fractional Clock Synchronization Without Phase Accumulator ROM
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Solution Overview
Problem
Conventional direct digital frequency synthesis (DDFS) techniques face limitations in achieving high resolution and low power consumption due to large read-only-memory (ROM) size requirements, offset errors, and trade-offs between distortion and spurious free dynamic range (SFDR), which restrict their application in portable devices.
Innovation Solution
The proposed solution involves a DDFS architecture that eliminates the need for a phase accumulator and look-up table, using a customized digital standard cell-based memory for coherent phase and frequency storage, with a phase rotator for sub-ppm resolution and a tunable common-mode correction circuit to adjust the duty cycle, allowing for fractional synchronization between the sampling clock and digital core clock without increasing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DDFS designs use phase accumulator and look-up table with increased resolution, then frequency resolution is improved, but chip area and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the phase accumulator and look-up table from the conventional DDFS architecture, retaining only the essential frequency control functionality. This removal of unnecessary components directly reduces chip area while maintaining frequency resolution through the simplified frequency control word mechanism.
Solution Approach 2:
The patent uses a simplified digital representation of frequency control information that copies only the essential parameters needed for frequency synthesis, rather than storing complete waveform data in large look-up tables. This reduces memory requirements and chip area while preserving the ability to achieve high frequency resolution.
2Measurement precision
If conventional DDFS designs use phase accumulator and look-up table with increased resolution, then frequency resolution is improved, but power consumption increases
Solution Approach 1:
By removing the power-intensive phase accumulator and large look-up table from the design, the patent significantly reduces dynamic power consumption associated with accessing and updating large memory structures, while maintaining frequency resolution through the streamlined frequency control approach.
Solution Approach 2:
The patent changes the operational parameters of the DDFS by using a more efficient frequency control mechanism that requires less computational resources and memory access, thereby reducing power consumption while achieving the same or better frequency resolution.
3Device complexity
If conventional DDFS designs use fixed duty cycle output, then circuit simplicity is maintained, but flexibility and adaptability are reduced
Solution Approach 1:
The patent introduces dynamic controllability of the duty cycle through the frequency control word mechanism, allowing the output waveform characteristics to be adjusted in real-time without adding complex separate control circuits. This enables adaptability while maintaining relative circuit simplicity.
Solution Approach 2:
The frequency control word serves multiple functions simultaneously: it controls the output frequency, phase, and duty cycle. This multi-functionality provides flexibility and adaptability without requiring separate dedicated circuits for each parameter, thus maintaining circuit simplicity.
4Adaptability or versatility
If conventional DDFS designs use external controller for duty cycle adjustment, then flexibility is improved, but device complexity increases
Solution Approach 1:
The patent merges the duty cycle control functionality into the existing frequency control word structure, eliminating the need for separate external controllers. This integration reduces overall device complexity while maintaining the flexibility to adjust duty cycle through the unified control mechanism.
Solution Approach 2:
The DDFS circuit serves itself by using the same frequency control word to simultaneously control frequency, phase, and duty cycle parameters. This self-service approach eliminates external controllers and reduces system complexity while maintaining full flexibility in parameter adjustment.
Data Source
AI summary
Described are apparatus and methods for fractional synchronization using direct digital frequency synthesis (DDFS). A DDFS device includes a memory with N address spaces, a write port circuit configured to sequentially write a digital desired pattern into the N address spaces, a read port circuit configured to readout the digital desired pattern from the N address spaces using continuous sequential automatic addressing from 0 to N−1 at a memory operating frequency clock, where the memory operating frequency clock is based on a sampling frequency clock used for high-speed data processing, and an analog signal processing circuit configured to process a readout digital desired pattern into an analog representation; and output a synthesized frequency clock from the analog representation to a digital core, where the synthesized frequency clock is fractionally synchronized with the sampling frequency clock.