DDFS LO Calibration for Downconverter Mixer Mismatch
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Solution Overview
Problem
Conventional downconverters face limitations in signal-to-noise and distortion ratio (SNDR) due to second-order nonlinearity issues caused by switch mismatches in mixers, which require complex analog calibration methods involving DC bias voltage tuning and decoupling components.
Innovation Solution
A digital frequency synthesis circuit generates all local oscillator (LO) frequencies from a single clock frequency, allowing digital-side calibration without additional analog components like capacitors and resistors, thereby improving matching and reducing parasitic effects, leading to a more compact and cost-effective mixer design with enhanced SNDR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If DC bias voltage tuning is used to compensate switch mismatch in conventional mixers, then matching between mixer cells is improved, but device complexity increases due to required decoupling capacitors and resistors
Solution Approach 1:
The patent replaces the analog mechanical/electrical calibration system (DC bias voltage tuning with decoupling capacitors and resistors) with a digital calibration system. The DDFS generates LO signals with programmable frequencies and phases, and digital calibration is achieved by adjusting digital control words rather than physical analog components. This eliminates the need for decoupling capacitors and resistors while maintaining matching between mixer cells.
Solution Approach 2:
The patent changes the calibration approach from adjusting DC bias voltages (analog parameter) to adjusting digital control words in the DDFS (digital parameter). The LO signal characteristics (frequency, phase) are controlled by digital parameters stored in lookup tables, allowing precise calibration without additional analog components. This parameter transformation from analog to digital domain resolves the contradiction between matching precision and device complexity.
2Manufacturing precision
If analog calibration components are added to the mixer, then switch mismatch compensation is improved, but the mixer layout area increases
Solution Approach 1:
The patent substitutes analog calibration components (capacitors, resistors) with a digital calibration implementation in the DDFS. The LO signals are generated digitally with programmable characteristics, and calibration is achieved through digital control words rather than physical analog components. This eliminates the need for additional layout area in the mixer while maintaining switch mismatch compensation capability.
Solution Approach 2:
The patent extracts the calibration function from the analog mixer domain and relocates it to the digital DDFS domain. By removing the requirement for decoupling capacitors and resistors from the mixer layout, the calibration functionality is achieved purely through digital signal generation and control, thereby reducing the mixer layout area while preserving mismatch compensation.
3Adaptability or versatility
If multiple LO frequencies are generated using conventional methods, then frequency flexibility is improved, but parasitic effects increase due to additional analog components
Solution Approach 1:
The patent implements a universal DDFS-based LO signal generation system that can produce multiple frequencies and phases from a single clock source. The DDFS uses programmable lookup tables and digital control to generate any required LO frequency, replacing multiple analog frequency sources and their associated decoupling components. This multi-functional digital approach reduces parasitic effects while maintaining frequency flexibility.
Solution Approach 2:
The patent replaces conventional analog frequency synthesis methods (which require multiple oscillators and decoupling components for each frequency) with a digital frequency synthesis system. The DDFS generates all LO frequencies digitally from a single clock, eliminating the need for multiple analog frequency sources and their associated parasitic-inducing decoupling capacitors and resistors.
Data Source
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AI summary
The invention relates to a DDFS (100) for generating a LO signal for a down converter (300). The DDFS (100) includes an l-path and a Q-path, and obtains a register output value, and generates a phase slope signal by adding a FCW to the register output value. Further, the phase slope signal is converted to a LO signal and a calibration code value (IIP2CAL_I, IIP2CAL_Q) is added to the LO signal. Finally, a phase shifted LO signal including the calibration code value (IIP2CAL_I, IIP2CAL_Q) is generated by phase shifting the LO signal including the calibration code value (IIP2CAL_I, IIP2CAL_Q). Thereby, all desired LO frequencies can be generated from a single clock frequency and the LO signal waveform can be freely chosen. Moreover, no additional components such as decoupling capacitors and resistors are needed on the analog side in the mixer of the down converter. Furthermore, the invention also relates to a mixer, a down converter and a corresponding method.