Test Board for DDI ESD Stress Reproduction
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Solution Overview
Problem
The operational reliability of Display Driver ICs (DDIs) is compromised due to electrostatic discharge (ESD) and electrical overstress (EOS) phenomena, making it difficult to reproduce defects, which hampers testing and validation.
Innovation Solution
A test board and system are designed with a substrate, mounting pads, and test terminals to simulate ESD stress using an RC equivalent circuit model, allowing for the reproduction of DDI defects by applying stress signals to semiconductor chips with specific terminal configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD stress is applied to DDI in a mounted state, then operational reliability testing is performed, but defect reproduction becomes difficult due to transient nature of ESD
Solution Approach 1:
The test board applies preliminary ESD stress to the DDI before final mounting in the electronic device. By performing stress testing on the test board with predetermined ESD models (HVM/QC models) before the DDI is installed in the actual product, the system can reproduce and identify defects early in the manufacturing process, avoiding the difficulty of reproducing transient ESD defects after mounting.
Solution Approach 2:
The test board serves as an intermediary between the ESD simulator and the DDI. It provides a controlled environment with specific circuit configurations (resistors, capacitors, grounding paths) that mediate the ESD stress application, allowing standardized reproduction of ESD conditions that would be difficult to achieve directly on the mounted DDI.
2Measurement precision
If complex ESD modeling is implemented to reproduce defects, then measurement precision improves, but device complexity increases
Solution Approach 1:
The test board divides the ESD testing function into separate, modular components: different ESD model circuits (HVM model with specific R-C values, QC model with different R-C values), separate test terminal groups, and distinct mounting areas. Each segment handles a specific aspect of ESD testing, making the overall complex system manageable through functional decomposition.
Solution Approach 2:
The test board utilizes parameter changes in resistance and capacitance values to create different ESD models. By adjusting R and C values in the ESD circuit paths, the system can switch between HVM and QC models without changing the physical structure, thereby managing complexity through electrical parameter variation rather than structural complexity.
3Adaptability or versatility
If multiple test terminal groups are arranged on substrate, then adaptability for different terminal configurations improves, but manufacturing precision requirements increase
Solution Approach 1:
The test board is designed with multiple test terminal groups that can accommodate different terminal configurations of various DDI models. The same test board structure serves multiple functions by supporting different pin assignments and terminal arrangements, allowing a single board design to test multiple device types through configurable connections rather than requiring dedicated boards for each device variant.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables reliable reproduction of DDI defects, enhancing the testing process and improving the operational reliability of semiconductor devices by accurately simulating ESD-induced stress, thereby facilitating defect analysis and validation.
Implementation Method 1
the ESD is discharge phenomenon in which a finite amount of positive charge may rapidly move between two objects having different potentials
Implementation Method 2
an RC equivalent circuit model to generate a stress signal
Data Source
AI summary
A test board for a semiconductor device and a test board including the same are provided. A test board includes a substrate, a mounting pad which is formed on the substrate and on which a semiconductor chip is mounted and a test terminal group arranged on the substrate to be spaced apart from the mounting pad and electrically connected to the semiconductor chip by a pattern arranged on the substrate, wherein the semiconductor chip includes a first terminal and a second terminal for inputting/outputting signals, the test terminal group includes a first test terminal electrically connected to the first terminal and a second test terminal electrically connected to the second terminal, a first voltage is applied to the first terminal and the second terminal, and a stress signal that is caused by a second voltage is applied to the first test terminal.