Display Driver IC Gate Clock Stabilization
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Solution Overview
Problem
The unstable ON time length of the gate clock signal in display panels due to phase changes causes fluctuations in pixel charging time, leading to abnormal display.
Innovation Solution
A display driver IC that generates an internal horizontal synchronization signal based on horizontal synchronization information, counting specific time lengths from a horizontal synchronization pulse to stabilize the gate clock signal's phase, ensuring consistent ON time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate clock signal phase is adjusted to synchronize with HSS tag, then the display panel can be driven, but the ON time length of gate clock signal becomes unstable
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the counting time lengths in a lookup table before actual operation. The synchronization signal generating circuit retrieves the appropriate counting time lengths from the table based on the horizontal synchronization tag, eliminating the need for real-time calculation and ensuring stable ON time length while maintaining phase synchronization.
Solution Approach 2:
The patent implements feedback through the synchronization signal generating circuit that continuously monitors the horizontal synchronization tag and adjusts the gate clock signal generation accordingly. The circuit uses feedback from the MIPI data stream to dynamically select counting time lengths, ensuring the gate clock signal maintains stable ON time length despite phase variations in the synchronization signal.
2Reliability
If the gate clock signal phase transitions frequently to synchronize with HSS, then synchronization is maintained, but pixel charging time fluctuates
Solution Approach 1:
The patent applies preliminary action by pre-storing counting time lengths in a lookup table structure. The synchronization signal generating circuit retrieves the appropriate counting time length from the table based on the horizontal synchronization tag, eliminating real-time calculation variations and ensuring consistent pixel charging time while maintaining accurate synchronization.
Solution Approach 2:
The patent changes the parameter approach by transitioning from dynamic phase adjustment to fixed counting time length selection. The synchronization signal generating circuit selects from pre-defined counting time lengths stored in the lookup table, converting the variable phase transition problem into a discrete parameter selection solution that ensures charging time consistency.
3Reliability
If counting time lengths are calculated in real-time, then the gate clock signal can be synchronized, but the processing complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing counting time lengths in a lookup table before actual operation. This transforms the real-time calculation requirement into a simple table lookup operation, significantly reducing processing complexity while maintaining synchronization stability.
Solution Approach 2:
The patent replaces the complex real-time calculation mechanism with a simpler lookup table retrieval mechanism. Instead of performing complex time length calculations during operation, the synchronization signal generating circuit simply retrieves pre-computed values from the lookup table, reducing processing complexity while ensuring synchronization stability.
Data Source
AI summary
A display driver integrated circuit (DDIC) receives a data stream, where the data stream includes display frame data, vertical synchronization information, and horizontal synchronization information. The DDIC generates an internal horizontal synchronization signal based on the horizontal synchronization information. The DDIC starts counting a first counting time length and a second counting time length from a same horizontal synchronization pulse of the internal horizontal synchronization signal, where the first counting time length is less than a horizontal time length defined by the internal horizontal synchronization signal, and the second counting time length is greater than the horizontal time length. At the end of the first counting time length, the DDIC pulls a gate clock signal from a first level to a second level. At the end of the second counting time length, the DDIC pulls the gate clock signal back from the second level to the first level.