DDIC Timing Control for Always-On Display Tearing

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Solution Overview

Problem

Electronic devices in always-on-display mode experience an unwanted tearing effect due to the processor being in a sleep state, which prevents it from recognizing scanned images, leading to display issues when multiple frames are displayed on a single screen.

Innovation Solution

An electronic device with a display driver integrated circuit (DDIC) that scans and displays images while the processor is in a sleep state, using a timing signal to synchronize the image output based on the completion of scanning, preventing the tearing effect by adjusting the timing signal transmission according to the location of displayed images.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the processor operates in sleep state to reduce power consumption, then power consumption is reduced, but the processor cannot recognize scanned images causing tearing effect

Engineering Contradiction:
Improvepower consumptionVSAvoiddisplay quality
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The DDIC acts as an intermediary between the sleep-state processor and the display panel. It independently scans and buffers image data in its internal memory, then outputs synchronized timing signals to coordinate frame completion with the display refresh rate, preventing tearing while keeping the processor in low-power mode

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The DDIC performs self-service by autonomously handling image scanning, buffering, and timing signal generation without requiring processor intervention. It manages the entire display output process independently, allowing the processor to remain in sleep state while maintaining reliable display output

Inventive Principle:
Principle #25Self-service

2Reliability

If the processor remains in active state to recognize and control displayed images, then display quality is maintained, but power consumption increases

Engineering Contradiction:
Improvedisplay qualityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The image scanning and timing control functions are extracted from the main processor and transferred to the DDIC. This allows the processor to be taken out of the active state for display operations, reducing its power consumption while the DDIC handles these tasks independently

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If multiple frames are displayed simultaneously on a single screen, then animation can be provided, but tearing effect occurs when processor is in sleep state

Engineering Contradiction:
Improveanimation capabilityVSAvoiddisplay quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The DDIC performs preliminary action by pre-scanning and buffering multiple frames of image data in its internal memory before display. This allows it to sequentially output complete frames synchronized with the display refresh rate, enabling animation while preventing tearing effects

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The DDIC uses periodic action by generating timing signals at regular intervals corresponding to the display refresh rate. It scans and outputs image frames periodically, ensuring each complete frame is displayed atomically without tearing, while maintaining smooth animation

Inventive Principle:
Principle #19Periodic action

Data Source

PatentEP3688747B1Electronic device and method for controlling output timing of signal corresponding to state in which content can be received based on display location of content displayed on display
Publication Date: 2022.11.09 SAMSUNG ELECTRONICS CO LTD
  • EP3688747B1 patent drawingFigure 1
  • EP3688747B1 patent drawingFigure 2
  • EP3688747B1 patent drawingFigure 3~4

AI summary

An electronic device includes a display panel; a processor; and display driving integrated circuitry (DDIC). The DDIC is configured to control the display panel and includes an internal memory. The DDIC is configured to receive, from the processor while the processor operates in an active state, a first content including a plurality of images to be displayed based on a specified order through the display panel while the processor operates in a low-power state; store the first content in the internal memory; change a timing for outputting a signal corresponding to a state capable of receiving a second content based on a change of a location in which an image among the plurality of images is displayed through the display panel while the processor operates in the low-power state; and output the signal to the processor based on the changed timing.