Data Direct I/O Cache Allocation for Disaggregated Die Systems
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Solution Overview
Problem
In multi-die, disaggregated systems, data movement between processor cores and I/O agents across different dies in a SoC leads to high data access latencies and interconnect power consumption, along with inefficient memory and die-to-die bandwidth usage, due to reliance on shared memory side caches and system memory.
Innovation Solution
Implementing Data Direct I/O (DDIO) modes that allow data to be processed directly between I/O agents and processor cores without invoking memory access, using an intermediate cache hierarchy that includes a shared last-level cache (L3 cache) or an IO$ cache, which can dynamically or statically allocate cache lines based on workload requirements and packet hints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is moved through shared memory side cache and system memory between I/O agent and processor core, then data communication is enabled, but data access latency increases and processing speed decreases
Solution Approach 1:
The patent extracts data from the traditional memory-based communication path (system memory and shared cache) and creates a direct data movement path between the I/O agent and processor core through the interconnect fabric, eliminating unnecessary memory access steps and reducing latency
Solution Approach 2:
The patent introduces an intermediary mechanism (the data movement engine and cache line allocation system) that enables direct data transfer between I/O agent and processor core without requiring data to reside in system memory or shared cache, thus reducing access latency while maintaining data integrity
2Reliability
If data is moved through multiple paths across interconnect fabric and EMIB boundaries, then data communication between dies is enabled, but interconnect power consumption increases
Solution Approach 1:
The patent performs preliminary actions by pre-allocating cache lines and establishing data movement paths before actual data transfer occurs. This allows the system to optimize the data path in advance, selecting the most energy-efficient route across the interconnect fabric and EMIB boundaries while ensuring reliable communication
Solution Approach 2:
The patent changes the operational parameters of the data movement system by dynamically selecting between different data paths and transmission modes based on workload characteristics, allowing the system to minimize power consumption while maintaining communication reliability across die boundaries
3Productivity
If shared memory and die-to-die interconnect bandwidth are used for data movement, then data transfer is enabled, but bandwidth consumption increases causing congestion
Solution Approach 1:
The patent segments the data transfer process into direct I/O path transfers and memory-based transfers, allowing data to be moved directly between I/O agents and processor cores without consuming shared memory bandwidth or die-to-die interconnect resources, thereby reducing overall bandwidth consumption and preventing congestion
4Reliability
If traditional memory-based data movement is used, then data communication is achieved, but processing efficiency decreases
Solution Approach 1:
The patent extracts data from the memory-based communication pathway and establishes a direct data movement channel between I/O agents and processor cores, eliminating the overhead of memory access operations while maintaining data communication reliability through controlled cache line allocation and data movement protocols
Data Source
AI summary
Examples include techniques associated with data movement to a cache in a disaggregated die system. Examples include circuitry at a first die receiving and granting requests to move data to a first cache resident on the first die or to a second cache resident on a second die that also includes a core of a processor. The granting of the request based, at least in part, on a traffic source type associated with a source of the request.