Double Data Rate ADC Comparator for Low-Power High Dynamic Range
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Solution Overview
Problem
Modern mobile communication devices require energy-efficient wide bandwidth analog to digital converters (ADCs) that support flexible multimode operation and have low power consumption, while traditional ΔΣ ADCs face issues with high power consumption, sensitivity to environmental variations, and manufacturing process variability.
Innovation Solution
A double data rate interpolating analog to digital converter (ADC) that operates on both edges of a clock cycle, utilizing a double data rate comparator core and set-reset flip-flop circuit to reduce power consumption and sensitivity to environmental variations, combined with time-based interpolation and folding techniques to achieve lower area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional high order loop filter with low resolution quantization is used, then dynamic range is improved, but power consumption increases and sensitivity to environmental variations worsens
Solution Approach 1:
The patent changes the resolution parameter of the quantizer from low (1-4 bits) to high (6 bits or more), which fundamentally alters the system architecture. This parameter change enables the use of a lower order loop filter, thereby reducing power consumption while maintaining high dynamic range through the higher resolution quantization process
Solution Approach 2:
The patent divides the quantization process into multiple stages using interpolation and folding techniques. The high resolution quantizer is segmented into multiple comparators that operate in parallel, with interpolation circuits that divide the input range into segments. This segmentation allows high dynamic range to be achieved through coordinated operation of multiple lower-complexity components rather than a single high-order filter
2Measurement precision
If higher resolution quantizer is used, then dynamic range is improved, but area and power consumption worsen
Solution Approach 1:
The high resolution quantizer is segmented into multiple comparators that operate in parallel, with interpolation circuits that divide the input range into segments. This segmentation allows high dynamic range to be achieved through coordinated operation of multiple lower-complexity components rather than a single high-order filter
Solution Approach 2:
The patent introduces time-based interpolation that operates in the time domain rather than purely in the voltage domain. By folding the input signal in time and using multiple comparators to process different time segments, the system achieves high resolution without requiring a single large-scale comparator, thus reducing overall area
3Use of energy by moving object
If time-based interpolation and folding techniques are used, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent merges the functions of multiple comparators, interpolation circuits, and folding logic into a unified quantizer architecture. The time-based interpolation and folding operations are combined with the comparison process itself, allowing the system to achieve high resolution and low power consumption through integrated operation rather than separate functional blocks
Solution Approach 2:
The patent employs periodic sampling and time-based interpolation where the quantizer operates in periodic phases. The folding technique periodically maps input values into a reduced range, and interpolation periodically reconstructs the full resolution information. This periodic operation allows complex high-resolution functionality to be achieved through repeated simple operations rather than continuously complex processing
Data Source
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AI summary
A double data rate comparator includes a double data rate comparator core, the comparator core configured to compare a voltage of an input signal to a reference signal during each of a rising edge and a falling edge in a single clock cycle of a clock input to the comparator core; and a double data rate set-reset flip flop circuit, the set-reset flip flop circuit comprising a set input and 5 a reset input connected to respective outputs of the double data rate comparator core, the set-reset flip flop circuit configured to perform a set-reset operation during the rising edge in the single clock cycle and the falling edge in the single clock cycle.