DDR Memory Address ECC for Burst Misaddress Detection
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Solution Overview
Problem
Conventional error correction methods for DDR SDRAMs are inadequate in identifying and correcting address line errors and poison-bit-indicated errors, often resulting in uncorrectable errors and false corrections, while also reducing the number of bits available for ECC parity bits.
Innovation Solution
A method that involves concatenating bits of the burst-write or read address, or their hash, with data blocks to create segments for SECDED error correction, generating parity bits, and using these to form FEC blocks without including the original address or hash, allowing for effective identification and correction of address errors without reducing ECC parity bit storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction methods use a single bit from the ECC parity field to denote a poison-bit marker, then poison-bit marking is achieved, but the number of bits available for ECC parity is reduced
Solution Approach 1:
The patent segments the address bits and distributes them across multiple data blocks within a burst. Each data block receives a portion of the address bits, and each segment is independently encoded with full ECC parity bits. This segmentation allows the system to maintain complete ECC protection for each block while still enabling poison-bit marking through the distributed address information.
Solution Approach 2:
The patent moves the poison-bit marking mechanism from the vertical dimension (reducing parity bits) to the horizontal dimension (expanding address bit distribution across multiple blocks). By concatenating address bits to multiple data blocks rather than using a single parity bit, the system achieves poison-bit marking capability while preserving the full complement of ECC parity bits for error correction.
2Reliability
If conventional error correction methods flip bits from the burst block as poison-bit markers, then poison-bit marking is achieved, but the marked block becomes indistinguishable from normal undecodable blocks resulting in false corrections
Solution Approach 1:
The patent applies local quality by making each data block's address segment unique and locally identifiable. Each block contains a specific portion of the address bits that can be independently verified against the expected address pattern. This localized address embedding allows the system to precisely identify which specific block is poisoned without affecting the interpretability of other blocks, thereby eliminating false corrections.
Solution Approach 2:
The patent implements feedback through the ECC decoding process that checks the consistency of address bits with the expected address pattern for each block. When a block is decoded, the address bits embedded in that block are verified against the known good address pattern. If mismatch detected, the block is identified as poisoned with high precision, and this feedback information is used to prevent false corrections while maintaining accurate error detection.
3Reliability
If address errors occur during read operations retrieving data from incorrect addresses, then data integrity is compromised, but conventional methods cannot reliably detect or correct these misaddresses
Solution Approach 1:
The patent applies preliminary action by embedding the address bits into each data block during the write operation. This pre-embedding of address information creates a reference pattern that can be used later for verification. When a read operation occurs, the embedded address bits in each block can be compared against the expected address pattern to detect misaddresses before data processing continues, enabling reliable detection of address errors that would otherwise go undetected.
Data Source
AI summary
A method for memory protection includes receiving a burst-write instruction that includes data and a burst-write address. The data are segmented into a plurality of data blocks. One or more bits of the burst-write address, or a hash of the burst-write address are concatenated to respective data blocks to obtain data-and-write-address-bit (DWAB) segments. A SECDED ECC is executed on respective DWAB segments to generate a corresponding plurality of sets of parity bits (DWAB-PB). Respective DWAB-PB are concatenated to the corresponding data block to generate corresponding forward-error-correction (FEC) blocks, none of the FEC blocks including the burst-write address or the hash of the burst-write address. A burst-write command and a respective portion of a respective FEC block is sent to respective memory devices during a plurality of beats until all of the beats of the burst-write have been sent.