DDR Memory Interface BIST Circuit Phase Measurement
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Solution Overview
Problem
Conventional automated test equipment (ATE) is inadequate for testing DDR memory interfaces due to limitations in handling high-speed data transmission and accurately measuring the phase difference between data and strobe signals, leading to signal degradation and increased costs, as well as the inability to test multiple memory devices simultaneously.
Innovation Solution
A built-in-self-test (BIST) memory interface circuit with a signal multiplier, multiplexers, digitally controlled delay line blocks, and a phase detector to measure the phase difference between data and strobe signals, allowing for internal testing and minimizing external equipment requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional automated test equipment (ATE) is used to test DDR memory interfaces, then testing capability is provided, but the equipment cannot accurately handle high-speed data transmission and measure phase difference, leading to signal degradation and increased costs
Solution Approach 1:
The DDR memory interface circuit performs self-testing through built-in test mode circuitry that generates test patterns, captures data and strobe signals, and measures phase difference internally. This eliminates the need for complex external ATE modifications while achieving accurate phase measurement through the phase detector and delay line blocks integrated within the memory interface itself.
Solution Approach 2:
A phase detector circuit serves as an intermediary between the data and strobe signals, converting the phase difference measurement into a quantifiable output. The delay line blocks act as intermediaries to generate multiple phase-shifted versions of the strobe signal, enabling precise phase difference determination without requiring complex external measurement equipment.
2Reliability
If external ATE is used for testing, then testing can be performed, but additional pins are required and signal degradation occurs due to routing sensitive signals externally
Solution Approach 1:
The testing function is extracted from the external ATE and integrated directly into the memory interface circuit. The test mode circuitry, phase detector, and delay line blocks are embedded within the device, allowing phase measurement to be performed internally without routing sensitive data and strobe signals through external connections, thereby maintaining signal integrity.
Solution Approach 2:
The testing functionality is merged with the normal operational circuitry of the memory interface. The same data and strobe signal paths used during normal operation are utilized during test mode, eliminating the need for separate external test signal routing and reducing the number of required external connections while maintaining signal integrity.
3Productivity
If conventional ATE is used, then testing is limited to fewer devices simultaneously, but modifying ATE for DDR support is not cost effective
Solution Approach 1:
Each memory interface circuit performs its own phase measurement and testing internally, allowing multiple devices to be tested simultaneously using standard ATE without requiring expensive modifications. The built-in test mode circuitry generates test patterns and captures results independently in each device, enabling high-volume parallel testing at minimal additional cost.
Data Source
AI summary
An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal. A phase detector determines a phase difference between the selected internal data strobe input signal and the selected phase shifted data strobe output signal and outputs a phase difference value.