DDR Buffer Device Equalization Using In-Band Signaling

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Solution Overview

Problem

Existing buffer self-training modes in DDR technology are limited to using sideband signals, which are slow and inaccessible during mission mode, preventing effective equalization during runtime.

Innovation Solution

Implementing device equalization self-training mode (DESTM) controls using in-band signaling, which allows for self-training of data buffers during mission mode by sending linear-feedback shift register (LFSR) patterns and waiting for a minimum completion time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If sideband signals are used for buffer self-training mode, then equalization training can be performed, but the training speed is slow and inaccessible during mission mode

Engineering Contradiction:
Improveequalization training capabilityVSAvoidtraining speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent introduces in-band signaling as an intermediary mechanism to enable buffer self-training during mission mode. Instead of relying solely on sideband signals, the host processor uses in-band signaling to communicate DESTM controls to the memory device, allowing equalization training to proceed at full operational speed without requiring separate slow sideband communication channels.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent makes the signaling mechanism universal by allowing the same in-band data channel to serve dual purposes: normal data transmission and equalization training control. The DESTM controls are embedded within the existing data interface, eliminating the need for dedicated training-only channels and enabling training operations during mission mode without compromising data transfer functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If buffer self-training mode is enabled using sideband signals only, then equalization can be performed, but host system capabilities are limited

Engineering Contradiction:
Improveequalization capabilityVSAvoidhost system capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent extends the applicability of buffer self-training to all host systems by using the universal in-band signaling interface that exists in all DDR memory systems. Any host processor communicating with DDR memory can initiate and control DESTM through standard in-band signaling, eliminating the limitation of requiring specialized sideband signal access and making the feature universally applicable across different host architectures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces dynamic control of the equalization training process through host processor intervention. The host can configure DESTM controls, adjust minimum duration parameters, and manage training timing based on system needs, transforming the static, sideband-dependent training mechanism into a dynamic, host-controllable process that adapts to various operational requirements.

Inventive Principle:
Principle #15Dynamics

3Productivity

If in-band signaling is used for DESTM controls, then training can occur during mission mode with faster processing, but additional control mechanisms are required

Engineering Contradiction:
Improvetraining speedVSAvoidcontrol mechanism complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the equalization training control functions with the existing data transmission interface. By embedding DESTM controls within the standard in-band signaling pathway used for normal data operations, the patent eliminates the need for separate control infrastructure. The same data channels and timing mechanisms used for data transfer are repurposed to carry training commands and status information, reducing overall system complexity despite the enhanced functionality.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250139004A1DDR buffer device equalization for self-training mode
Publication Date: 2025.05.01 ADVANCED MICRO DEVICES INC
  • US20250139004A1 patent drawing
  • US20250139004A1 patent drawing
  • US20250139004A1 patent drawing

AI summary

Embodiments herein describe a method and system for configuring device equalization self-training mode (DESTM) controls using in-band signaling, the DESTM controls including at least setting a minimum duration time, using a host to enable the DESTM controls, triggering a buffer to perform a self-training mode, sending linear-feedback shift register (LFSR) patterns to the buffer for the minimum duration time, and waiting for the minimum completion time to end before disabling the DESTM. The minimum duration time indicates a time that the self-training mode is active and is predefined. The buffer executes the self-training mode within the predefined minimum duration time.