DDR Subsystem Power Reduction via Cache Hit Rate Feedback
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Solution Overview
Problem
Portable computing devices face significant power consumption issues due to high DDR system power usage, particularly from unpredictable memory traffic patterns, which existing solutions fail to optimize effectively without compromising performance.
Innovation Solution
A system and method that includes a system resource manager on a SoC to determine memory performance requirements and adjust DDR subsystem access based on cache hit rates, dynamically controlling clock frequency and voltage to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the DDR subsystem operates at worst-case voltage and frequency to service unpredictable traffic, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic frequency and voltage adjustment in the DDR subsystem based on real-time cache hit rate monitoring. The system transitions from static worst-case operation to dynamic adaptation, adjusting operational parameters according to actual traffic patterns and cache performance, thereby reducing power consumption while maintaining reliability when needed.
Solution Approach 2:
The system employs feedback mechanisms by monitoring cache hit rates and using this information to adjust DDR subsystem operating parameters. The resource manager receives cache performance data and dynamically modifies frequency and voltage settings, creating a closed-loop control system that optimizes power consumption based on actual system state.
2Use of energy by moving object
If the DDR clock frequency is adjusted conservatively to avoid performance drops, then power savings are achieved, but productivity decreases
Solution Approach 1:
The system uses cache hit rate feedback to intelligently adjust frequency settings. When cache hit rates are high, the DDR frequency can be reduced conservatively without impacting performance. When cache hit rates drop, the system automatically increases frequency to maintain productivity, creating a performance-aware power management strategy.
Solution Approach 2:
The patent dynamically changes operational parameters (frequency, voltage) based on cache performance metrics. By monitoring cache hit rates and adjusting DDR subsystem parameters accordingly, the system achieves power savings during high-cache-hit periods while maintaining high performance during cache-miss-intensive workloads.
3Use of energy by moving object
If a system cache is incorporated to reduce DDR traffic, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent implements a nested memory hierarchy with the system cache embedded within the DDR subsystem structure. The cache is integrated into the existing memory controller architecture, allowing it to intercept and satisfy memory requests before they reach the external DRAM, thereby reducing DDR traffic and power consumption without requiring a completely separate memory system.
Solution Approach 2:
The system cache provides self-service functionality by automatically intercepting and satisfying memory access requests that can be fulfilled from cached data. This eliminates the need for complex external memory transactions for frequently accessed data, reducing DDR traffic and power consumption while maintaining simple integration with the existing memory subsystem.
Data Source
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AI summary
Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem controls a DDR clock frequency based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.