DDR Chip-Kill Recovery via Parallel ECC Erasure Decoding
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Solution Overview
Problem
DDR memory devices are prone to chip-kill events, leading to data loss, and existing error correction methods require prior notice of failure to recover information, which is not feasible with increasing bit-error rates and high-speed operations.
Innovation Solution
A low-latency forward-error correction method using an array of ECC erasure decoders operating in parallel to identify and correct chip-kill events without prior notice, employing a decode selection logic circuit to determine the correct decoder based on excess symbol corrections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Reed-Solomon erasure decoding is used to recover lost information from chip-kill events, then data recovery capability is improved, but the system requires external information indicating which portion of data needs to be erased, which increases system complexity and latency
Solution Approach 1:
The system performs self-diagnosis by having multiple ECC decoders independently decode the same data block and compare results. The decoders autonomously identify which chip has failed through majority voting without requiring external intervention or prior knowledge of failure location, thus enabling self-service error correction
Solution Approach 2:
Multiple ECC decoders are pre-configured and ready to operate in parallel before any failure occurs. When a chip-kill event happens, the system immediately activates the preliminary decoding structure without needing to first identify the failed chip, reducing recovery latency
2Measurement precision
If Reed-Solomon erasure decoding is used with external failure notification, then decoding accuracy is improved, but recovery latency increases due to the need for prior notice of failure
Solution Approach 1:
The system prepares multiple ECC decoders in advance, each configured to potentially decode data assuming a different chip has failed. When a chip-kill event occurs, the pre-positioned decoders can immediately begin work without waiting for failure identification, achieving both accuracy and low latency
Solution Approach 2:
The system implements a feedback mechanism where decoder outputs are compared and validated. The correct decoder's output is identified through majority voting or consistency checking, providing feedback that confirms accurate decoding without requiring external failure notification
3Productivity
If multiple ECC decoders operate in parallel to identify chip-kill events, then recovery speed is improved, but device complexity increases
Solution Approach 1:
The error correction function is segmented into multiple independent ECC decoders, each handling a specific hypothesis about which chip has failed. This segmentation allows parallel processing of different failure scenarios, improving recovery speed while keeping each individual decoder relatively simple
Solution Approach 2:
Multiple ECC decoders are implemented with identical circuitry and logic, making them universal components that can handle any chip failure scenario. This multi-functionality approach reduces overall system complexity by repeating a proven simple design rather than creating a complex custom decoder
Data Source
AI summary
A system and method for double data rate (DDR) chip-kill decoding using an array of ECC erasure decoders operating in parallel to identify a location of a chip-kill event associated with a DDR memory device. The ECC erasure decoder that correctly identifies the chip-kill location is then used to decode subsequent DDR bursts transmitted from the DDR memory device.