DDR Clock Delay Line Measurement for Stable Phase Shifting
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Solution Overview
Problem
Existing clock signal measurement circuits struggle to provide a compensated percentage-of-clock period delay signal that remains stable under varying clock frequencies and process, voltage, and temperature conditions, especially in Double Data Rate (DDR) SDRAM applications where data strobe signals need to be phase-shifted by 90°.
Innovation Solution
The implementation of a variable digital delay line responsive to digital control words, coupled with a capture stage and controller, allows for the generation of a variably delayed clock signal, enabling measurement of the clock signal period and providing a compensated percentage-of-clock period delay, while reducing metastability and allowing for post-processing to ensure accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed delay value is used for data strobe signal phase shifting, then the circuit is simple, but the delay accuracy deteriorates under varying clock frequencies and PVT conditions
Solution Approach 1:
The patent implements a dynamic delay adjustment mechanism where the delay value is no longer fixed but can be adjusted based on operating conditions. A measurement circuit determines the actual clock period, and a control circuit dynamically adjusts the delay through a delay element (such as a variable delay line or programmable delay circuit) to maintain accurate 50% or other percentage-based phase shifts despite variations in clock frequency, process, voltage, and temperature conditions.
Solution Approach 2:
The patent changes the delay parameter dynamically by adjusting the delay element's delay amount based on measured clock period and operating conditions. The control circuit modifies the delay parameter (e.g., through a digital control word for a programmable delay line) to compensate for PVT variations and clock frequency changes, ensuring the delay remains proportional to the clock period rather than being a fixed value.
2Measurement precision
If a variable delay circuit is implemented to compensate for clock frequency changes, then the delay accuracy improves, but the device complexity increases
Solution Approach 1:
The patent implements a self-adjusting system where the measurement circuit automatically measures the clock period and feeds this information to the control circuit, which then automatically adjusts the delay element without external intervention. This closed-loop self-service mechanism eliminates the need for manual calibration or external control, reducing the operational complexity despite adding measurement and control components.
Solution Approach 2:
The patent incorporates a feedback loop where the measurement circuit continuously monitors the clock period and feeds this information back to the control circuit, which adjusts the delay element accordingly. This feedback mechanism ensures that the delay remains accurately proportional to the clock period under varying conditions, improving delay accuracy while using a systematic approach to manage the added circuit complexity.
3Ease of operation
If the data strobe signal is edge aligned with data signals, then the capture timing is simplified, but the data valid window becomes narrower
Solution Approach 1:
The patent dynamically adjusts the phase relationship between the data strobe signal and data signals by implementing variable delay on the strobe signal. Instead of a fixed edge-aligned configuration, the delay element allows the strobe to be phase-shifted by a variable amount (e.g., 50% of clock period) to optimize the capture timing window, balancing the simplicity of edge-aligned capture with the need for an adequate data valid window.
Data Source
AI summary
Circuits for measuring a clock signal include a variable digital delay line that is configured to delay the clock signal by variable amounts in response to variable values of a digital control word that are applied thereto, to produce a variably delayed clock signal. A capture stage is responsive to the variably delayed clock signal and to the clock signal to capture a logic state of the variably delayed clock signal during transitions of the clock signal. A controller is configured to generate the variable values of the digital control word that are applied to the variable digital delay line and to identify a value of the digital control word in response to the capture stage capturing a change in the logic state of the variably delayed clock signal during a transition of the clock signal. Related methods and memory devices are also described.