Delay-Locked Loop Circuit for Precise DDR Clock Duty Cycle
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Solution Overview
Problem
Existing double data rate clock signals are sensitive to changes in integrated circuit process parameters and temperature, leading to asymmetrical noise margins and increased data error rates, particularly at high frequencies, due to variations in duty cycle.
Innovation Solution
A delay locked loop circuit with a phase detector and two delay circuits is used to automatically correct the duty cycle of double data rate clock signals, ensuring a predetermined duty cycle, such as 50%, by adjusting the delay between the data clock and synchronization signals, using a second delay circuit with current starved inverter circuitry and operational amplifier feedback to maintain precise timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If double data rate clock signals are used to double the effective bandwidth, then the clock frequency can be reduced to one half of the data rate, but the duty cycle must be precisely 50% to avoid asymmetrical noise margins and data errors
Solution Approach 1:
The patent employs a delay-locked loop (DLL) circuit that continuously monitors the duty cycle of the double data rate clock signal and automatically adjusts delay elements to maintain precisely 50% duty cycle. The feedback mechanism compares the actual duty cycle against the target value and dynamically compensates for variations caused by process parameters and temperature changes, thereby resolving the contradiction between achieving high bandwidth and maintaining precise duty cycle control.
Solution Approach 2:
The invention changes the delay parameters of circuit elements within the DLL to dynamically adjust and maintain the duty cycle at 50%. By varying the delay introduced by controllable delay elements in response to detected duty cycle deviations, the system adapts to process and temperature variations while preserving the desired 50% duty cycle, thus enabling high-speed operation without data errors.
2Reliability
If the duty cycle of double data rate clock signals varies due to parameter variations in inverters, then asymmetrical noise margins occur, but maintaining precise 50% duty cycle requires complex control circuitry
Solution Approach 1:
The delay-locked loop implements continuous feedback monitoring of the duty cycle and automatic adjustment of delay elements. This closed-loop control detects duty cycle deviations caused by inverter parameter variations and compensates in real-time, maintaining asymmetrical noise margins at acceptable levels without requiring overly complex external control circuitry. The feedback mechanism integrates the control function within the clock generation system itself.
Solution Approach 2:
The DLL circuit is self-regulating, automatically detecting and correcting its own duty cycle deviations without external intervention. The circuit monitors its output clock signal and adjusts its internal delay elements autonomously to maintain 50% duty cycle, thereby improving reliability while avoiding the need for additional complex external control circuitry.
3Speed
If high frequency double data rate clock signals are used, then the system speed increases, but asymmetrical timing becomes critical and more difficult to control
Solution Approach 1:
The patent employs a delay-locked loop that continuously monitors the duty cycle of high-frequency clock signals and automatically adjusts delay elements to maintain precisely 50% duty cycle. This feedback mechanism compensates for timing asymmetries that become critical at high frequencies, ensuring that rising and falling edges provide equal timing margins despite process and temperature variations.
Solution Approach 2:
The invention dynamically changes the delay parameters of circuit elements within the DLL to maintain symmetrical timing at high frequencies. By adjusting the delay introduced by controllable delay elements in response to detected duty cycle deviations, the system adapts to maintain precise timing accuracy even as operating frequency increases and timing margins become more critical.
Data Source
AI summary
A delay locked loop includes a storage element coupled to a data bus and produces a data synchronization signal. A phase detector receives a data clock signal and the data synchronization signal and produces a delay control signal. A first delay circuit produces a signal which is delayed relative to the data clock signal according to the delay control signal. A second delay circuit receiving the delayed signal produces a control signal coupled to a control input of the storage element by delaying the delayed signal an amount which causes the control signal to have a predetermined duty cycle.