DDR Data Output Clock Duty Correction for Skew Control
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Solution Overview
Problem
In DDR SDRAM systems, skew differences in rising and falling clocks due to PVT variations and transistor characteristics lead to distorted duty ratios of the data strobe signal, resulting in reduced timing margins and potential incorrect data reception during high-speed operations.
Innovation Solution
A data output circuit with delay control blocks that generate clock delay signals in response to power-up and reset signals, allowing for the correction of duty ratios of rising and falling clocks, and trigger units that ensure stable data output clocks by controlling delays and skew differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the data strobe signal is generated using conventional clock circuits, then the circuit structure is simple, but the duty ratio becomes distorted due to skew differences in rising and falling clocks caused by PVT variation and transistor characteristics
Solution Approach 1:
The patent implements dynamic delay adjustment for rising and falling clocks using control signals that adapt to PVT variations. The delay circuits are configured to dynamically compensate for skew differences, ensuring the duty ratio meets specification requirements under varying process, voltage, and temperature conditions while maintaining a relatively simple overall circuit structure.
2Ease of operation
If the duty ratio of the clock is not accurately controlled, then the circuit operation is simple, but the timing margin is reduced and incorrect data may be received during high-speed operation
Solution Approach 1:
The patent applies preliminary delay adjustment to the rising and falling clocks before they are combined to generate the data strobe signal. By pre-compensating for potential skew differences through controlled delay circuits, the duty ratio is ensured to meet specification requirements in advance, preventing timing violations and ensuring reliable data reception during high-speed operations.
3Manufacturing precision
If delay control circuits are added to correct clock duty ratios, then the duty ratio accuracy is improved, but the device complexity increases
Solution Approach 1:
The patent applies delay control selectively and locally to only the rising and falling clock paths that require compensation. Rather than implementing comprehensive control across the entire system, the delay circuits are targeted specifically at the clock generation stage where skew differences occur, achieving duty ratio correction with minimal additional circuit complexity.
Data Source
AI summary
A data output circuit according to one embodiment of the present invention includes: a delay control block configured to generate a clock delay signal in response to a power-up signal and a reset signal; a first delay block configured to correct a duty ratio of a rising clock according to the clock delay signal and output the corrected rising clock; and a second delay block configured to correct a duty ratio of a falling clock according to the clock delay signal and output the corrected falling clock.