DDR Clock Multiplexing for Precise Duty Cycle Control
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Solution Overview
Problem
Conventional DDR circuits suffer from poor duty cycle of output data due to unbalanced pull-up and pull-down drive strengths, leading to timing mismatches and increased error rates.
Innovation Solution
A double data rate circuit with a clock generator, clock divider, and multiplexer that generate complementary and multiphase clock signals with balanced drive strengths, ensuring equal timing delays and phase differences, and a multiplexer that multiplexes data bits using these signals to achieve precise duty cycle control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional DDR circuit uses unbalanced pull-up and pull-down drive strengths, then circuit complexity is reduced, but duty cycle precision deteriorates
Solution Approach 1:
The patent applies asymmetry principle by using different drive strengths for pull-up and pull-down circuits. Specifically, the pull-up circuit uses a first drive strength while the pull-down circuit uses a second drive strength that is different from the first, allowing compensation for process variations and achievement of precise 50% duty cycle without requiring perfectly symmetric circuit design.
Solution Approach 2:
The patent changes the drive strength parameter of the pull-up and pull-down circuits to achieve precise duty cycle control. By adjusting the drive strengths independently and selecting appropriate values to compensate for process variations, the circuit achieves accurate 50% duty cycle output despite conventional design limitations.
2Device complexity
If clock signal has poor duty cycle, then circuit design is simplified, but timing performance deteriorates
Solution Approach 1:
The patent implements feedback mechanism by using a duty cycle control circuit that monitors the output duty cycle and adjusts the drive strengths of pull-up and pull-down circuits accordingly. This feedback ensures the clock signal maintains precise 50% duty cycle, improving timing performance and reliability while maintaining manageable circuit design complexity.
Solution Approach 2:
The patent makes the drive strengths dynamic by allowing them to be adjusted based on process variations and operating conditions. The pull-up and pull-down circuits can dynamically change their drive strengths to compensate for variations, ensuring consistent timing performance across different manufacturing batches and operating environments.
3Ease of manufacture
If pull-up and pull-down drive strengths are unbalanced, then manufacturing process is simpler, but timing skew increases
Solution Approach 1:
The patent changes the drive strength parameters of pull-up and pull-down circuits to specific values that compensate for process variations. By independently setting these parameters and selecting values that balance the overall drive strengths, the circuit achieves minimal timing skew while maintaining ease of manufacturing through standard CMOS processes.
Data Source
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AI summary
A double data rate circuit includes a clock generator, a clock divider and a multiplexer. The clock generator is used to receive a source clock signal to generate a pair of complementary clock signals. The clock divider is coupled to the clock generator, and used to generate four multiphase clock signals using only single-edge transitions of the pair of complementary clock signals. The four multiphase clock signals are successively out-of-phase by 90°. The multiplexer is coupled to the clock divider, and used to multiplex multiple data bits into an output data stream by sequentially selecting and deselecting each data bit of the multiple data bits upon a first edge transition of and a second edge transition of two of the four multiphase clock signals, respectively, and outputting each selected data bit as the output data stream.