DDR Clock Gating That Holds State Without False Clock Transitions
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Solution Overview
Problem
Existing clock gating solutions are ineffective for double data rate (DDR) logic, as they only operate on single data rate (SDR) logic, leading to inefficiencies in power management in modern integrated circuits.
Innovation Solution
A system and method that include a DDR clock gate configured to pass or hold a DDR clock input based on a clock enable control, allowing for efficient clock gating in DDR logic, and a SDR-to-DDR converter module that transitions the clock output on the triggering edge of the SDR clock to produce a DDR clock output at half the frequency, enabling power savings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If existing clock gating solutions are used on SDR logic, then power consumption is reduced, but they cannot be applied to DDR logic leading to continued power waste
Solution Approach 1:
The patent changes the operational parameters of clock gating from single-edge triggering (SDR) to double-edge triggering (DDR). The DDR clock gate circuit responds to both rising and falling edges of the clock signal, effectively doubling the gating opportunities per clock cycle while maintaining compatibility with DDR logic's dual-edge operation mode
Solution Approach 2:
The invention creates a universal clock gating mechanism that can handle both SDR and DDR logic types. The DDR clock gate serves multiple functions: it gates clock signals for DDR logic, converts SDR clocks to DDR clocks, and provides state holding capability during disabled periods, making it adaptable to various logic types
2Use of energy by moving object
If clock gating is implemented to disable unused logic units, then power consumption decreases, but the clock frequency must be reduced which may impact performance
Solution Approach 1:
The DDR clock gate utilizes periodic double-edge triggering, capturing clock transitions on both rising and falling edges. This periodic dual-edge operation allows the gate to function at effectively twice the frequency of traditional SDR gates, maintaining higher operational speeds while enabling aggressive power management through selective gating
3Use of energy by moving object
If the DDR clock gate holds state when disabled, then power consumption is minimized, but the clock signal is completely stopped which may affect signal integrity
Solution Approach 1:
The DDR clock gate acts as an intermediary between the clock source and the gated logic. When disabled, it holds its internal state rather than completely blocking the signal path, maintaining signal integrity while preventing clock transitions from reaching the gated logic. This intermediary function allows power savings without compromising the underlying signal infrastructure
Data Source
AI summary
Methods, systems, and computer program products are provided to implement clock gating with double data rate (“DDR”) logic. In traditional single data rate (“SDR”) clock gating, disabling the clock holds the clock logic level to a predefined value, potentially causing a logic transition that would be erroneously interpreted as a normal clock transition by DDR logic. Similar techniques can also be utilized to convert a SDR clock to a half-frequency DDR clock for use with DDR logic, realizing the energy efficiencies of DDR clocking.