DDR Clock Duty-Cycle Correction With MDLL Edge Delay Control
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Solution Overview
Problem
Existing duty-cycle correction methods fail to maintain a consistent 50% duty-cycle across process, voltage, and temperature variations in DDR systems, often introducing jitter and failing to achieve precise alignment of clock signals, especially with multiple clocks.
Innovation Solution
A method and circuit that utilize a Master Delay Locked Loop (MDLL) code to set a fixed rising-edge delay and adjust the falling-edge delay within a specific range to achieve a 50% duty-cycle, ensuring consistent duty-cycle correction across varying PVT conditions by using a combination of coarse and fine delay elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple delay stages are added to correct duty-cycle for largest PVT variations, then duty-cycle correction coverage is improved, but signal jitter increases and 50% duty-cycle achievement becomes less likely
Solution Approach 1:
The duty-cycle correction is divided into two independent segments: rising-edge correction and falling-edge correction. The rising-edge delay is fixed at X (percentage of MDLL code), while the falling-edge delay is variable (0 to NX). This segmentation allows each edge to be optimized independently, achieving 50% duty-cycle across PVT variations without introducing excessive jitter from overly complex delay networks.
Solution Approach 2:
The invention changes the delay parameter from a large fixed number of stages to a smaller fixed delay X multiplied by a calibration factor N. The falling-edge delay is adjusted within a controlled range (0 to NX) based on detected duty-cycle requirements. This parameter transformation reduces the total number of delay stages needed while maintaining correction effectiveness across PVT conditions.
2Manufacturing precision
If rising edges of multiple clocks are shifted by different amounts for duty-cycle correction, then individual duty-cycle correction is improved, but edge alignment and timing correlation amongst clocks are lost
Solution Approach 1:
The invention applies the same fixed rising-edge delay X (derived from MDLL code) to all clock signals in the system. This homogeneous treatment of rising edges preserves edge alignment and timing correlation amongst multiple clocks, while the falling-edge delay is individually adjusted only when necessary to achieve 50% duty-cycle without disrupting the synchronized rising edges.
3Stability of the object's composition
If rising edge is shifted by a fixed amount to maintain edge alignment, then timing correlation amongst clocks is preserved, but duty-cycle correction effectiveness decreases under PVT variations
Solution Approach 1:
The invention makes the falling-edge delay dynamic and adjustable within the range 0 to NX, while keeping the rising-edge delay fixed at X. This dynamic adjustment of the falling edge allows the duty-cycle to be corrected for PVT variations, while the fixed rising edge maintains edge alignment amongst multiple clocks. The detector monitors duty-cycle and controls the falling-edge delay accordingly.
4Adaptability or versatility
If delay stages are increased to cover largest PVT variations, then adaptability to PVT conditions is improved, but the number of components and circuit complexity increases
Solution Approach 1:
The delay correction is segmented into a fixed rising-edge component (X) and a variable falling-edge component (0 to NX). This segmentation reduces the total number of delay stages needed compared to using many stages for both edges, while still providing adequate coverage for PVT variations through the calibrated variable component.
Solution Approach 2:
The invention transforms the delay correction approach by using a calibrated parameter N (integer from detector) to scale the variable falling-edge delay range. This parameter change allows the system to adapt to PVT variations using a controlled number of delay stages rather than requiring a large fixed number of stages for all possible conditions.
Data Source
AI summary
A method for performing duty-cycle correction of an output clock in a Double Data Rate (DDR) system includes: setting a fixed delay of a rising-edge of the output clock as a parameter X which is equal to a digital Master Delay Locked Loop (MDLL) code of the DDR system multiplied by a percentage representing an estimated distortion of the duty-cycle of the output clock from a desired duty-cycle; shifting the rising-edge of the output clock by the fixed delay; and determining whether a duty cycle of the shifted output clock meets the desired duty-cycle. When a duty-cycle of the shifted output clock meets the desired duty-cycle, the fixed rising-edge delay is taken as a final delay code for the output clock; otherwise, a falling-edge of the output clock is shifted by an amount in a range between 0 and NX, wherein N is an integer.