Duty Cycle Correction Loop Offset Cancellation in DDR Clocking
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Solution Overview
Problem
Duty cycle correction circuits introduce intrinsic offsets that hinder accurate correction of duty cycle errors in double data rate systems, making it difficult to maintain timing margins and performance.
Innovation Solution
An electronic device with a duty cycle corrector that calculates an offset code by averaging duty cycle correction codes from both a clock signal and its complementary signal, and negates this offset to improve correction accuracy, using a multiplexer and finite state machine to selectively output and retransmit signals for precise adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If duty cycle correction circuits are used to mitigate clock duty cycle error, then duty cycle accuracy is improved, but intrinsic offset is introduced that hinders achievable correction
Solution Approach 1:
The patent applies preliminary action by measuring and storing duty cycle correction codes for both the clock signal and its complement before actual operation. These pre-measured codes are then used to calculate and compensate for intrinsic offsets in advance, allowing the system to correct for these harmful factors before they degrade performance.
Solution Approach 2:
The patent uses the complementary clock signal as a copy that mirrors the original clock signal's characteristics. By measuring duty cycle correction codes on both the original and complementary signals, the system can compare and differentiate between actual duty cycle errors and intrinsic offsets introduced by the correction circuitry itself.
2Reliability
If duty cycle correction codes are applied to correct duty cycle error, then timing margins are improved, but intrinsic offset reduces achievable correction
Solution Approach 1:
The patent implements feedback by continuously monitoring the duty cycle correction codes generated for both clock and complement signals, comparing these codes to detect intrinsic offsets, and then adjusting the correction applied to subsequent clock cycles. This closed-loop feedback mechanism ensures that timing margins are maintained while compensating for the harmful intrinsic offset.
3Measurement precision
If offset code is calculated by averaging duty cycle correction codes, then offset cancellation accuracy is improved, but calculation complexity increases
Solution Approach 1:
The patent changes the parameter representation by working with duty cycle correction codes that are already in a digital, discrete format. This allows the offset calculation to be performed through simple digital averaging operations rather than complex analog measurements, achieving high offset cancellation accuracy while minimizing calculation complexity.
Data Source
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AI summary
An electronic device (300) includes a clock (302) configured to transmit a first clock signal (CKIN) and a second clock signal (/CKIN) for operation of the electronic device; a duty cycle corrector (304, 308, 310) coupled to the clock (302) to correct a duty cycle of the first and second clock signals, the duty cycle corrector (304, 308, 310) being configured to: assign and store a first duty cycle correction code in response to the first clock signal (CKIN); assign and store a second duty cycle correction code in response to the second clock signal (/CKIN); calculate an offset code based on the first and second duty cycle correction codes; and negate the offset code from results of duty cycle correction operations.