DDR Memory Controller Clock Phase Adjustment
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Solution Overview
Problem
The complexity of achieving the required timing relationship between DDR SDRAM controllers and memory devices increases with performance, particularly during write operations, due to uncertainty in data placement relative to the data strobe (DQS), leading to reduced memory throughput and potential phase constraint violations.
Innovation Solution
A memory controller system that uses a system clock with programmable delay elements and multiplexers to shift data relative to the data strobe, ensuring proper alignment and phase compliance during write operations, thereby maintaining data transmission integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission speed is increased to improve memory throughput, then productivity is improved, but timing precision deteriorates due to uncertainty in data placement relative to DQS
Solution Approach 1:
The patent applies preliminary action by delaying the DQS signal in advance before it reaches the memory device. The controller introduces a programmable delay to the DQS signal path, allowing the data and strobe signals to arrive at the memory device with proper timing alignment. This pre-delay compensates for the uncertainty in data placement relative to DQS, ensuring that even at high transmission speeds, the timing relationship between data and strobe remains precise at the memory device input.
2Manufacturing precision
If complex delay circuitry is added to each DRAM device to achieve proper timing alignment, then timing precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts the delay function from individual DRAM devices and consolidates it in the memory controller. Instead of requiring complex delay circuitry in each memory device, the controller generates a single delayed DQS signal that is distributed to all memory devices. This approach maintains precise timing alignment while significantly reducing the complexity burden on individual memory devices and simplifying the overall system architecture.
3Quantity of substance
If routing lengths are extended to accommodate more data signals, then quantity of substance is improved, but timing precision deteriorates due to increased skew and jitter
Solution Approach 1:
The patent introduces the delayed DQS signal as an intermediary that mediates the timing relationship between data signals and memory device sampling. By delaying the strobe signal rather than attempting to perfectly balance all data signal routing lengths, the system can accommodate wider data buses with more signals without proportionally increasing skew and jitter. The delayed DQS acts as a reference that synchronizes data sampling across all bus lines.
Data Source
AI summary
A computer system for writing data to a memory is disclosed. The memory controller in the computer system comprises a system clock, which is generated by the memory controller. A first register captures the lower data word based on the rising edge of the system clock. A second register, coupled to the first register, captures the output of the first register based on the rising edge of the system clock. A third register, captures the upper data word based on the falling edge of the system clock. A forth register, coupled to the third register, captures the output of the third register based on the falling edge of the system clock. A first multiplexer is coupled to a forth register and a second register. A delay element, coupled to the system clock and a first multiplexer, adjusts the phase of the system clock. A second multiplexer, coupled to the system clock, generates a data strobe.