DDR Memory Controller Timing Calibration via DQS Delay
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Solution Overview
Problem
Existing DDR memory controllers face challenges in efficiently capturing and processing memory data due to timing inconsistencies and high silicon real estate requirements, necessitating a solution that can adapt to system-level timing irregularities and power supply voltage variations while minimizing latency and silicon usage.
Innovation Solution
A DDR memory controller that utilizes core domain clocking mechanisms and programmable delay elements for the dqs signal, with self-configuring logic to dynamically adjust capture clock timing and CAS latency compensation, reducing the need for delay elements on dq inputs and allowing calibration during both power-up and system operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delay elements are added to dq inputs to compensate for timing skew, then timing accuracy is improved, but silicon real estate increases
Solution Approach 1:
The patent extracts the delay compensation function from the dq input path and relocates it to the DQS clock path. By placing delay elements only on the DQS signal rather than on each dq data line, the solution maintains timing skew compensation capability while significantly reducing the total number of delay elements required, thus lowering silicon real estate consumption.
Solution Approach 2:
The delay elements on the DQS signal serve multiple functions simultaneously: they compensate for timing skew affecting all dq lines, enable proper alignment between clock and data edges, and provide a single point of control for timing calibration. This multi-functional approach replaces what would otherwise require multiple separate delay elements on each dq line.
2Adaptability or versatility
If self-configuring logic is implemented to dynamically adjust timing, then adaptability to timing variations is improved, but device complexity increases
Solution Approach 1:
The patent implements self-configuring logic that automatically calibrates the delay elements during power-up and system operation. The logic monitors timing relationships and autonomously adjusts the delay settings without requiring external intervention or complex control mechanisms, thereby achieving high adaptability while keeping the overall device complexity manageable.
Solution Approach 2:
The self-configuring logic performs preliminary calibration of the delay elements during power-up before normal operation begins. This preliminary action establishes optimal timing settings in advance, allowing the system to adapt to process variations and timing skew without requiring complex real-time adjustment mechanisms during data operation.
3Reliability
If calibration is performed during power-up and system operation, then reliability of data capture is improved, but loss of time due to calibration increases
Solution Approach 1:
The patent implements calibration at two distinct periods: an initial calibration during power-up to establish baseline timing settings, and subsequent calibration during system operation to compensate for drift and environmental changes. This periodic approach ensures high reliability of data capture while distributing calibration time across different operational phases rather than requiring continuous calibration.
Solution Approach 2:
By performing initial calibration during power-up before normal data operations begin, the patent establishes optimal timing settings in advance. This preliminary calibration reduces the need for frequent calibration during operation, thereby minimizing the loss of time due to calibration while maintaining high reliability of data capture throughout system operation.
Data Source
AI summary
A computer-implemented method includes an act of configuring hardware to cause at least a part of the hardware to operate as a double data rate (DDR) memory controller, and to produce a capture clock to time a read data path, where a timing of the capture clock is based on a first clock signal of a first clock, delay the first clock signal to produce a delayed first clock signal, adjust the delay such that at least one clock edge of the delayed first clock signal is placed nearer to at least one clock edge of at least one data strobe (DQS), or at least one signal dependent on a DQS timing, and produce a modified timing of the capture clock based on the delay of the first clock signal.