DDR Memory Controller Re-training Without Data Loss
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Solution Overview
Problem
Storage devices face challenges in maintaining data integrity during intermittent failures of the memory subsystem, such as resets or power loss, which can lead to data loss in cache memory subsystems, especially in high-reliability applications.
Innovation Solution
A method is introduced to re-train a DDR memory controller in a storage device without resetting the memory devices, by enabling self-refresh mode and manually refreshing contents using a processor, ensuring data retention during re-training.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory subsystem is reset to eliminate error conditions, then the memory controller can be re-trained, but user data in the cache memory is lost
Solution Approach 1:
The system segments the reset operation into two independent parts: resetting only the memory controller while preserving the memory devices. This is achieved by providing separate reset signals to the memory controller and memory devices, allowing selective resetting of the controller without affecting cached data in the memory devices.
Solution Approach 2:
The system performs preliminary actions to preserve data before re-training: enabling self-refresh mode in memory devices to maintain data during controller reset, and configuring the memory devices to retain their contents. This preliminary preparation ensures data integrity throughout the controller re-training process.
2Adaptability or versatility
If the memory controller is re-trained during operation, then intermittent failures can be corrected, but data integrity may be compromised
Solution Approach 1:
The system prepares protective measures in advance before attempting controller re-training: enabling self-refresh mode and configuring memory devices to maintain data. This cushioning mechanism ensures that even if re-training fails or causes interruptions, the cached data remains protected and intact.
Solution Approach 2:
The system implements feedback mechanisms to monitor the success of controller re-training operations. Based on feedback from the re-training process, the system can determine whether to continue normal operations or initiate alternative recovery procedures, thereby maintaining data integrity through adaptive response to re-training outcomes.
3Device complexity
If a single reset signal is used for both memory controller and memory devices, then the reset mechanism is simple, but data loss occurs during controller reset
Solution Approach 1:
The reset mechanism is segmented into separate control paths: one reset signal path for the memory controller and another independent path for memory devices. This segmentation allows the controller to be reset without affecting the memory devices, eliminating data loss while maintaining relatively simple overall system architecture.
Data Source
AI summary
Methods and structure for enabling re-training of a DDR memory controller in a storage device without loss of data in the DDR memory devices of the cache memory in response to detecting failure of the memory subsystem during operation of the storage device. In response to detecting a failure of the memory subsystem, the memory controller is reset without resetting the memory devices. The memory controller is then re-trained for operation with the memory device. During the re-training, self-refresh mode of the memory devices is disabled and manual refresh is performed by a processor of the storage device to thereby retain any user data in the memory device.