DDR Counter Circuit for Low-Power High-Speed ADC Counting
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Solution Overview
Problem
High-speed counters in CMOS image sensors, such as ripple counters, consume excessive power due to frequent toggling of the least significant bit (LSB), which is undesirable for reducing overall power consumption in analog-to-digital converters (ADCs) and image sensors.
Innovation Solution
A double data rate (DDR) counter design is implemented, where the first stage is positive edge-triggered and subsequent stages are negative edge-triggered, reducing the toggling frequency of the LSB by utilizing both rising and falling edges of the clock signal, and incorporating a logic circuit for XOR operations and a count stop circuit to manage counting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed ripple counters are used in ADC for fast analog-to-digital conversion, then conversion speed is improved, but power consumption increases due to frequent LSB toggling
Solution Approach 1:
The counter is divided into multiple stages (first stage, second stage, third stage, etc.), where each stage processes different bits of the count value. The first stage generates the LSB and is triggered on one edge (e.g., rising edge), while subsequent stages generate other bits and are triggered on the opposite edge (e.g., falling edge). This segmentation allows the counter to operate at high speed while reducing the frequency of LSB toggling, thereby lowering power consumption.
Solution Approach 2:
The counter utilizes both rising and falling edges of the clock signal alternately for different stages. The first stage is triggered on one edge type while subsequent stages are triggered on the opposite edge type, creating a periodic pattern of operation. This periodic action effectively doubles the operating frequency without proportionally increasing power consumption, as each stage toggles less frequently than the clock frequency.
2Device complexity
If conventional single-edge-triggered counters are used, then circuit design is simple, but operating frequency is limited and power consumption is high
Solution Approach 1:
The counter is divided into multiple stages (first stage, second stage, third stage, etc.), where each stage processes different bits of the count value. The first stage generates the LSB and is triggered on one edge (e.g., rising edge), while subsequent stages generate other bits and are triggered on the opposite edge (e.g., falling edge). This segmentation allows the counter to operate at high speed while reducing the frequency of LSB toggling, thereby lowering power consumption.
Solution Approach 2:
The counter utilizes both rising and falling edges of the clock signal alternately for different stages. The first stage is triggered on one edge type while subsequent stages are triggered on the opposite edge type, creating a periodic pattern of operation. This periodic action effectively doubles the operating frequency without proportionally increasing power consumption, as each stage toggles less frequently than the clock frequency.
Data Source
AI summary
In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The first stage includes a first clock input and is edge-triggered on one of the rising and falling edges of a signal applied at the first clock input. The counter includes at least one second stage for generating another bit of the value in the counter. The second stage includes a second clock input and is edge-triggered on the other of the rising and falling edges of a signal applied at the second clock input.