DDR Counter Clock Latching to Prevent Missing Counts
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Solution Overview
Problem
Conventional image sensors face challenges in efficiently performing addition operations due to power consumption issues and missing counts in counter circuits, particularly in DDR counter circuits where the LSB is the input clock, leading to inefficiencies in counting periods and digital output generation.
Innovation Solution
The implementation of a DDR counter circuit with a latch stage that generates a latch stage output clock based on the enable signal and previous clock states, allowing for reduced power consumption and accurate counting by differentiating clock states, thereby addressing the inefficiencies in addition operations and missing counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional counter circuit is used for addition operations, then the counting process can be performed, but synchronization issues between the latch stage output clock and counter clock occur leading to missing counts
Solution Approach 1:
The patent implements a dynamic clock selection mechanism where the counter clock is selectively chosen from either the original counter clock or the inverted latch stage output clock based on synchronization requirements. This dynamic adaptation allows the circuit to switch between different clocking modes to prevent missing counts during addition operations while maintaining normal counting functionality.
Solution Approach 2:
The patent introduces a feedback mechanism where the latch stage output clock is generated based on the state of the counter clock at previous edges. This feedback loop ensures that the clock signals remain synchronized by continuously monitoring and adjusting the latch stage output clock phase and timing based on the counter clock state, thereby preventing synchronization issues and missing counts.
2Productivity
If the counter circuit operates at high speed to improve productivity, then the counting rate increases, but power consumption increases
Solution Approach 1:
The patent employs periodic clock gating where the counter clock is enabled only during necessary counting operations and disabled during idle periods. By periodically activating the clock signal based on operational requirements rather than running continuously at high speed, the circuit achieves high counting rates when needed while significantly reducing average power consumption during non-critical periods.
Data Source
AI summary
In at least one example embodiment, a counter circuit includes a latch stage configured to generate a latch stage output clock based on a first rising edge of an enable signal, a state of a counter clock at a previous falling edge of the enable signal, and a state of the output clock at the previous falling edge of the enable signal such that the latch stage output clock and the counter clock have a different state if the state of the counter clock at the previous falling edge and the state of the output clock at the previous falling edge are the same and such that the latch stage output clock and the counter clock have a same state if the state of the counter clock at the previous falling edge and the state of the output clock at the previous falling edge are different.