DDR Data Receiver Valid Window Expansion for Accurate Sampling
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Solution Overview
Problem
Conventional DDR memory data receiving apparatuses face inaccurate sampling results due to severe channel dispersion and insufficient signal transitions, especially with faster memory speeds, despite using over-sampling mechanisms.
Innovation Solution
Implement a data receiving apparatus with a data valid window expanding mechanism that performs AND and OR logic operations on input and delayed data signals, using multiplexers to select processed signals based on previous sampling results, and samples these signals at appropriate edges of a data strobe signal to enhance accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If over-sampling mechanism is used to perform data sampling, then sampling timing can be dynamically adjusted, but inaccurate sampling results still occur due to severe channel dispersion and insufficient signal transitions
Solution Approach 1:
The patent applies preliminary action by performing logic operations (AND/OR) on the input data signal and delayed data signal before the actual sampling operation. This pre-processing expands the valid data window and ensures that the signal has sufficient transitions and valid levels before sampling, thereby improving sampling accuracy despite channel dispersion effects
Solution Approach 2:
The patent introduces an intermediary mechanism by using logic operation circuits (AND gate, OR gate) between the data signal path and the sampling circuit. These intermediaries process the data signals to expand the valid window and provide more robust sampling inputs, acting as a mediator that compensates for channel dispersion effects
2Speed
If faster memory speed is implemented, then transmission speed increases, but channel dispersion becomes more severe and signal transitions become insufficient
Solution Approach 1:
The patent performs logic operations on the data signal and delayed data signal before sampling to expand the valid data window. This preliminary processing ensures that even at faster memory speeds with severe channel dispersion, the signal maintains sufficient transitions and valid levels for accurate sampling
Solution Approach 2:
The patent changes the parameter of signal validation by using logic operations to expand the valid data window. This transforms the signal characteristics to ensure sufficient transitions and valid levels, maintaining signal quality despite increased transmission speed and channel dispersion
3Measurement precision
If data valid window expanding mechanism is implemented using logic operations and multiplexers, then sampling accuracy improves, but device complexity increases
Solution Approach 1:
The patent segments the data processing function into distinct modules: data delay circuit, AND logic operation circuit, OR logic operation circuit, rising edge data selection circuit, falling edge data selection circuit, and sampling circuit. This segmentation allows each component to perform a specific function, improving sampling accuracy while making the overall system more manageable despite increased complexity
Data Source
AI summary
The present disclosure discloses a data receiving apparatus having data valid window expanding mechanism. An AND gate and an OR gate respectively perform logic operation on an input data signal and a delayed data signal delayed therefrom. A rising edge data multiplexer selects the OR gate processed signal and the AND gate processed signal respectively when a previous falling edge sampling result is at a low state and a high state to be outputted as a current rising edge data. A falling edge data multiplexer selects the OR gate processed signal and the AND gate processed signal respectively when a previous rising edge sampling result is at a low state and a high state to be outputted as a current falling edge data. A sampling circuit respectively performs rising and falling edge sampling on the current rising and the falling edge data to generate sampling results.