DDR Memory Decision Feedback Equalizer With 2UI Timing Path
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional decision feedback equalizers (DFE) in double data rate memory (DDR) are limited by heavy-loading adders and tight timing, restricting maximum data rate and critical path timing, especially in 16-nanometer processes.
Innovation Solution
A digital decision feedback equalizer (DFE) with a sampling circuit and adder circuit for parallel-to-serial conversion, allowing for second-order half-rate speculation and supporting multiple DDR modes, including DDR5 and LPDDR5, with a sampling circuit that separates even and odd bits and an adder circuit that combines them for full-rate data generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional analog DFE is used, then signal integrity is improved by reducing intersymbol interference, but the maximum data rate is limited due to heavy-loading adder
Solution Approach 1:
The patent replaces the conventional analog DFE with a digital DFE implementation. This substitution transforms the equalization function from the analog domain to the digital domain, allowing the use of digital adders and logic circuits that can operate at higher speeds while maintaining the ISI reduction capability through decision feedback mechanisms.
Solution Approach 2:
The patent changes the operating parameters of the DFE by implementing it in digital logic with parallel adders that can complete additions within half a UI. This parameter change in the adder operation speed and architecture enables the system to achieve higher data rates (6400 Mbps) while maintaining signal integrity through effective equalization.
2Device complexity
If a conventional digital DFE is used, then timing is simplified, but the critical path timing is limited to within one unit interval in 16-nanometer process
Solution Approach 1:
The patent segments the adder circuit into parallel adders that operate independently on different data paths. This segmentation allows each adder to complete its operation within half a UI rather than requiring the full UI, effectively doubling the achievable data rate while maintaining manageable timing complexity through modular design.
Solution Approach 2:
The patent implements preliminary action by performing adder operations in parallel ahead of the critical timing path constraints. The parallel adders complete their calculations within half UI, preparing the data in advance for subsequent processing stages, thereby extending the critical path timing beyond the traditional one UI limitation.
3Speed
If the sampling circuit is placed prior to the adder circuit, then the critical timing path is increased from 1UI to 2UI, but the circuit complexity increases
Solution Approach 1:
The patent introduces another dimension to the timing architecture by inserting a sampling circuit stage before the adder circuit. This dimensional change in the signal flow path allows the critical timing path to be extended from 1UI to 2UI, creating additional time for parallel adder operations while managing complexity through structured circuit design.
Data Source
AI summary
A decision feedback equalizer for double data rate memory is shown, which uses a sampling circuit and an adder circuit with parallel-to-serial conversion. The sampling circuit separates the sampling of a sampling object into even bits and odd bits, to output even-bit data on an even-bit channel, and to output odd-bit data on an odd-bit channel. The adder circuit with parallel-to-serial conversion is coupled to the sampling circuit to receive the even-bit data and the odd-bit data, and to combine the even-bit data with the odd-bit data to generate full-rate data.