DDR Memory Interface DFE Calibration Using Adaptive FIR Feedback
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The calibration of decision feedback equalizers (DFEs) in DDR memory systems is time-consuming due to the need for extensive hardware involvement, limiting the ability to achieve optimal filter coefficients within the allocated initialization time, which affects signal integrity and inter-symbol interference (ISI) in high-frequency data communication.
Innovation Solution
A signal processing method and device that utilizes a finite impulse response (FIR) filter with adaptive processing to determine optimal filter coefficients quickly by correlating digital output signals with error signals, employing algorithms like least mean square (LMS) and sign-sign LMS to minimize ISI, allowing for rapid calibration of DFEs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional sweeping calibration method is used for DFE, then optimal filter coefficients can be obtained, but calibration time becomes very long
Solution Approach 1:
The patent changes the calibration approach from traditional sweeping methods to decision feedback equalization with adaptive filtering. The filter coefficients are updated iteratively using feedback from detection errors, allowing the system to converge to optimal parameters much faster than exhaustive sweeping while maintaining or improving accuracy.
Solution Approach 2:
The patent implements decision feedback equalization where the detected signal is fed back through an adaptive filter that continuously adjusts its coefficients based on the difference between expected and actual values. This feedback mechanism enables rapid convergence to optimal filter settings without requiring time-consuming sweeping calibration.
2Reliability
If full memory controller involvement is used for calibration, then comprehensive hardware calibration is achieved, but initialization time is exceeded
Solution Approach 1:
The patent performs preliminary signal processing and equalization adjustments during normal operation rather than requiring complete calibration during initialization. The adaptive filter continuously refines coefficients based on incoming signals, ensuring comprehensive hardware calibration is achieved progressively rather than all at once during startup.
Solution Approach 2:
The patent transitions from static calibration (fixed coefficients determined during initialization) to dynamic calibration where filter coefficients continuously adapt during operation. This allows the system to achieve comprehensive calibration over time while maintaining fast initialization, as the equalization improves progressively with each incoming signal.
Data Source
AI summary
A signal processing method for a memory system interface circuit is provided. The memory system interface circuit comprises at least one signal pin each being configured to receive a transmission signal via an individual signal link and to generate a received signal at a receiving node of the signal link. The signal processing method comprises: pre-processing the received signal to obtain an input signal; removing a weighted feedback signal from the input signal to obtain an output signal, wherein the weighted feedback signal is provided by a finite impulse response (FIR) filter in a feedback path; deciding on the output signal based on a predetermined base signal to generate a digital output signal; weighting, on a scale of a filter coefficient matrix of the FIR filter, the digital output signal to obtain the weighted feedback signal; comparing the output signal with a reference signal to generate an error signal; and determining a set of optimal filter coefficients of the filter coefficient matrix of the FIR filter and the reference signal according to correlation between the digital output signal and the error signal, to minimize inter-symbol interference (ISI) of the received signal introduced by transmission characteristics of the signal link.