DDR Memory Interface With Differential Strobes for Crosstalk Control
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Solution Overview
Problem
Single-ended bi-directional source synchronous signal transmission in DDR DRAM interfaces faces severe crosstalk issues as data rates increase, affecting signal integrity, particularly in next-generation DDR interfaces exceeding 10 Gbps.
Innovation Solution
Implementing a memory system with bidirectional differential data and data strobe signal buses for data transmission between the memory controller and memory, combined with single-ended and bidirectional differential data strobe signal buses for internal memory interactions, utilizing modulation and demodulation circuits to convert between differential and single-ended signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If single-ended bi-directional source synchronous signal transmission is used in DDR DRAM interfaces, then the interface structure is simple and ease of manufacture is improved, but severe crosstalk issues occur as data rate increases, worsening signal integrity
Solution Approach 1:
The patent changes the signal transmission parameter from single-ended to differential mode. The memory controller and data buffer transmit data signals and data strobe signals in differential mode, which fundamentally alters the electrical characteristics to achieve better noise immunity and reduced crosstalk while maintaining the same interface functional structure
Solution Approach 2:
The patent introduces a data buffer as an intermediary component between the memory controller and the memory. This data buffer performs signal conversion between differential mode (for the memory controller interface) and single-ended mode (for the memory interface), acting as a mediator that enables the use of differential signaling where needed while maintaining compatibility with existing memory devices
2Productivity
If data rate is increased to improve productivity in next-generation DDR interfaces, then data transmission speed is improved, but crosstalk becomes a major factor affecting signal integrity, worsening transmission quality
Solution Approach 1:
The patent changes the signal transmission parameter from single-ended to differential mode. The memory controller and data buffer transmit data signals and data strobe signals in differential mode, which fundamentally alters the electrical characteristics to achieve better noise immunity and reduced crosstalk while maintaining the same interface functional structure
Solution Approach 2:
The patent introduces a data buffer as an intermediary component between the memory controller and the memory. This data buffer performs signal conversion between differential mode (for the memory controller interface) and single-ended mode (for the memory interface), acting as a mediator that enables the use of differential signaling where needed while maintaining compatibility with existing memory devices
Data Source
AI summary
The present application provides a memory system. The memory system includes a memory controller, a memory and a data buffer coupled between the memory controller and the memory. The memory controller and the data buffer are coupled to each other via a first data bus and a first data strobe signal bus. The first data strobe signal bus is used to transmit a first data strobe signal for sampling control of a first data signal. The first data strobe signal bus is a bidirectional differential signal bus. The memory and the data buffer are coupled to each other via a second data bus and a second data strobe signal bus. The second data strobe signal bus is used to transmit a second data strobe signal for sampling control of a second data signal. The second data strobe signal bus is a bidirectional differential signal bus.