DDR DQS Bus Control via Driver Voltage Stabilization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In DDR data transfer systems with parallel termination, the DQS bus often enters an unknown state when a device relinquishes control, making it difficult for devices to determine bus availability, especially at high frequencies or over long distances.
Innovation Solution
A driver is introduced to maintain the DQS bus voltage at a logical level, ensuring bus control by pulling the voltage to a recognizable state when no device is transmitting, using resistive means or enabling circuitry to manage this voltage, allowing for reliable bus availability determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel termination is used for DQS bus, then data transfer rate is improved, but bus voltage stability deteriorates causing unknown states between transmissions
Solution Approach 1:
The patent applies preliminary action by proactively driving the DQS bus to a known logical state (either logical 0 or logical 1) before another device takes control of the bus. This prevents the bus from entering an unknown drifted state between transmissions, ensuring that when a device relinquishes control, the bus is already in a predictable state that the next controlling device can reliably detect and use for synchronization.
2Productivity
If parallel termination is used for DQS bus, then data transfer rate is improved, but device complexity increases due to need for complex timing calculations
Solution Approach 1:
The patent implements self-service by having each device automatically drive the DQS bus to a known logical state upon relinquishing control. This self-driven state establishment eliminates the need for receiving devices to perform complex timing calculations to determine bus availability, as the bus state is self-evident and immediately detectable, simplifying the overall system operation.
3Productivity
If parallel termination is used for DQS bus, then data transfer rate is improved, but reliability deteriorates at high frequencies and long distances
Solution Approach 1:
The patent applies feedback by continuously maintaining the DQS bus in a known logical state through active driving by the non-controlling device. This feedback mechanism ensures that regardless of frequency or distance, the bus state remains predictable and detectable, providing reliable feedback to receiving devices about bus availability and eliminating the reliability issues associated with drifted unknown states in high-frequency or long-distance scenarios.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution simplifies and stabilizes DQS bus control, enabling more reliable data transfer by maintaining a logical state, reducing the need for complex timing calculations and improving reliability at high frequencies and over distances.
Implementation Method 1
The driver may include a first resistance between the clock bus and a voltage VDD and a second resistance between the clock bus and ground
Data Source
AI summary
Systems and techniques for improved bus control, which may be particularly useful for double data rate (DDR) data transfer. A circuit may include a clock transmitter in communication with a clock bus, a clock receiver in communication with the clock bus, and a driver in communication with the clock bus. The driver may drive a voltage of the clock bus to a first voltage level when the clock transmitter is not transmitting a clock signal on the clock bus and the clock receiver is not receiving a clock signal on the clock bus.