DDR DRAM Differential Receiver Output Control
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Solution Overview
Problem
Existing DDR DRAM interface systems face challenges in managing the differential signal pair (DQS_t and DQS_c) during idle periods, which can disrupt downstream digital logic, and in supporting various DRAM protocols with different pre-amble and post-amble patterns.
Innovation Solution
A method that measures the temporal gap between consecutive read bursts in a DDR DRAM storage device, generates a state code based on the gap length, and controls the output of the differential receiver accordingly, allowing for the gating off of unwanted outputs and supporting different DRAM protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the differential receiver continuously outputs signals during idle periods when DQS_t and DQS_c are at the same level, then the receiver is always ready to sample data, but downstream digital logic is disrupted by unknown output values
Solution Approach 1:
The patent applies preliminary action by determining the state of the differential signal pair before the idle period begins. The controller checks whether DQS_t and DQS_c are toggling differentially during the data readout period, and based on this preliminary determination, it proactively gates off the output during the subsequent idle period. This prevents unknown output values from disrupting downstream logic without requiring complex real-time monitoring during idle periods.
2Ease of operation
If the controller samples data on every toggling of DQS_t or DQS_c, then data capture is simplified, but false triggering occurs during pre-amble and post-amble portions where toggling is not used for data sampling
Solution Approach 1:
The patent segments the data strobe signal into distinct portions: pre-amble, data readout period, and post-amble. The data capture circuit is configured to sample data only during the data readout period when DQS_t and DQS_c are toggling differentially, while ignoring toggles during pre-amble and post-amble portions. This segmentation allows simplified sampling logic while maintaining sampling accuracy by restricting operation to the valid data window.
3Adaptability or versatility
If the controller supports all DRAM protocols with different pre-amble and post-amble patterns, then protocol compatibility is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal data capture circuit that works across multiple DRAM protocols by focusing on the common characteristic: sampling data when DQS_t and DQS_c toggle differentially during the data readout period. The controller receives an indication of the current DRAM protocol and configures the data capture circuit accordingly, but the fundamental sampling mechanism remains the same. This universal approach supports different pre-amble and post-amble patterns without requiring separate sampling logic for each protocol.
4Productivity
If read bursts are continuously transmitted without gaps, then data transfer efficiency is improved, but the system cannot handle idle periods between bursts where differential signal gating is needed
Solution Approach 1:
The patent implements dynamic output control that adapts to the transmission pattern. The controller continuously monitors the state of DQS_t and DQS_c and dynamically gates off the differential receiver output during idle periods between read bursts, while maintaining continuous operation during active data transfer. This dynamic adjustment allows the system to achieve high productivity during burst transmission while properly handling idle periods, preventing disruption to downstream logic.
Data Source
AI summary
Disclosed herein are systems, methods and devices for controlling output of a storage device during read operations. The method comprises: measuring a length of a temporal gap between first and second consecutive read bursts from a storage device, the first and second read burst are in response to first and second read commands received by the storage device, respectively; generating a state code according to the length, wherein the state code has a first value when the length is zero, a second value when the length is equal to or shorter than a threshold time length but is non-zero, and a third value when the length is greater than the threshold time length; and controlling output of the storage device according to the state code.