DDR Serial Encoder Synchronization for Low Output Skew
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Solution Overview
Problem
The existing Double Data Rate (DDR) serial encoder for Mobile Display Digital Interface (MDDI) links has a larger size and complexity due to a glitchless multiplexer and multiple logic layers, resulting in output skew and lower link rates.
Innovation Solution
A DDR serial encoder with a non-glitchless multiplexer and a single layer of logic between the final register stage and the encoder output, using a synchronizing circuit to ensure glitch-free output and reduce output skew, thereby simplifying the design and increasing link rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a glitchless multiplexer is used to ensure glitch-free output, then output reliability is improved, but encoder size and complexity increase
Solution Approach 1:
The patent extracts the glitch prevention function from the multiplexer itself and relocates it to a separate synchronizing circuit. This allows the multiplexer to be simplified to a basic data selection device, while the synchronizing circuit handles the complex timing and glitch prevention logic, thereby reducing overall encoder complexity while maintaining reliability.
Solution Approach 2:
The encoder is segmented into distinct functional blocks: a simplified multiplexer for data selection, a synchronizing circuit for timing control and glitch prevention, and output registers. This segmentation allows each component to be optimized independently, reducing the complexity of individual components while maintaining system-level reliability.
2Adaptability or versatility
If multiple logic layers are used between the final register stage and the encoder output, then design flexibility is improved, but output skew increases and link rate decreases
Solution Approach 1:
The patent extracts the timing synchronization function from the logic layers and concentrates it in a dedicated synchronizing circuit. This reduces the number of logic layers between the final register stage and encoder output to a minimum, thereby reducing propagation delay and output skew while maintaining design flexibility through the synchronizing circuit's configurable parameters.
3Device complexity
If a non-glitchless multiplexer is used to reduce size and complexity, then encoder size and complexity are reduced, but output glitches may occur
Solution Approach 1:
The patent introduces a synchronizing circuit as an intermediary between the non-glitchless multiplexer and the output registers. This synchronizing circuit acts as a mediator that cleans up timing issues and prevents glitches from propagating to the output, allowing the use of a simpler multiplexer while maintaining output reliability.
Solution Approach 2:
The synchronizing circuit performs preliminary timing alignment and synchronization of the multiplexer output before it reaches the output registers. By pre-synchronizing the signals and aligning them with the clock edges, the circuit prevents glitches from occurring at the final output, enabling the use of a simpler non-glitchless multiplexer.
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AI summary
A Double Data Rate (DDR) serial encoder is provided. In one aspect, the DDR serial encoder includes a non-glitchless multiplexer and digital logic for ensuring a glitch-free encoder output. By using a non-glitchless multiplexer, the size and complexity of the encoder is significantly reduced. In another aspect, the DDR serial encoder has a single layer of logic between the final register stage and the encoder output, thereby resulting in a reduced output skew and increased link rate.