DDR Serial Encoder Layout for Glitch-Free Low-Skew Output
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Solution Overview
Problem
The existing Double Data Rate (DDR) serial encoder for Mobile Display Digital Interface (MDDI) links has a larger size and complexity due to a glitchless multiplexer and multiple logic layers, leading to output skew and lower link rates.
Innovation Solution
A DDR serial encoder with a non-glitchless multiplexer and a single layer of logic between the final register stage and the encoder output, reducing the number of paths and simplifying output skew analysis, while ensuring a glitch-free encoder output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a glitchless multiplexer is used to ensure glitch-free output, then the reliability of the encoder output is improved, but the size and complexity of the encoder increases
Solution Approach 1:
Instead of using a complex glitchless multiplexer to prevent glitches at the source, the patent inverts the approach by using a simpler non-glitchless multiplexer and then removing glitches through a synchronizing circuit that samples the output at specific clock edges, thereby reducing overall encoder complexity while maintaining output reliability
Solution Approach 2:
The patent introduces a synchronizing circuit as an intermediary component between the non-glitchless multiplexer and the encoder output. This synchronizing circuit acts as a mediator that filters out glitches from the multiplexer output by sampling only at valid clock edges, thus protecting the final output without requiring the multiplexer itself to be glitchless
2Adaptability or versatility
If multiple logic layers are used between the final register stage and the encoder output, then the functionality of the encoder is improved, but the output skew increases and link rate decreases
Solution Approach 1:
The patent extracts the synchronizing function from the main data path by placing it in a separate parallel path. The synchronizing circuit operates independently to clean up the multiplexer output, allowing the main data path to remain short and fast while still achieving glitch-free output, thus reducing output skew and maintaining high link rates
Solution Approach 2:
The patent adds a temporal dimension to the solution by using time-multiplexed sampling in the synchronizing circuit. Instead of adding more logic layers in the spatial dimension (which会增加 skew), the solution uses time-based sampling at specific clock edges to achieve synchronization and glitch removal, effectively trading time for space to reduce critical path delay
Data Source
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AI summary
A Double Data Rate (DDR) serial encoder is provided. In one aspect, the DDR serial encoder includes a non-glitchless multiplexer and digital logic for ensuring a glitch-free encoder output. By using a non-glitchless multiplexer, the size and complexity of the encoder is significantly reduced. In another aspect, the DDR serial encoder has a single layer of logic between the final register stage and the encoder output and a reduced number of paths from the final register stage to the encoder output, thereby resulting in reduced output skew and increased link rate.