DDR FIFO Data Processing for Wireless Communication Testing
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Solution Overview
Problem
Existing wireless communication testing systems face inefficiencies in data transmission due to asynchronous clock domains, leading to long operation times and low data throughput rates, despite the high bandwidth capabilities of DDR interfaces.
Innovation Solution
The system implements large-scale FIFO data processing based on DDR, utilizing an ingress and egress asynchronous clock domain FIFO, a DDR4 AXI interface, and a flow control state machine to manage data flow and optimize clock domain synchronization, thereby achieving a unified FIFO operation mode that maximizes DDR interface bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asynchronous clock domain FIFO is used for data transmission between different clock domains, then data transmission reliability is improved, but operation time increases and data throughput rate decreases
Solution Approach 1:
The patent implements continuous data transmission between ingress and egress FIFOs by maintaining persistent write and read operations without idle cycles. The DDR interface continuously writes to the egress FIFO as long as data is available in the ingress FIFO, eliminating gaps in data flow and maximizing throughput while maintaining reliability through the asynchronous FIFO architecture.
Solution Approach 2:
The system pre-allocates DDR memory space for the egress FIFO and pre-configures the data transmission pipeline before actual data arrival. This preliminary setup ensures that when data arrives in the ingress FIFO, the transmission path is already prepared, reducing latency and improving overall data throughput without compromising transmission reliability.
2Quantity of substance
If traditional cache-then-read method is used for DDR data storage and retrieval, then data storage capacity is improved, but operation time increases and bandwidth utilization decreases
Solution Approach 1:
The patent merges the cache storage function and data retrieval function into a unified first-in-first-out operation mode. The same DDR memory space serves as both the cache for incoming data and the source for outgoing data, with a single unified FIFO control mechanism managing both write and read operations simultaneously, thereby reducing operation time and improving bandwidth utilization.
Solution Approach 2:
The unified FIFO control mechanism acts as an intermediary between the DDR memory and the data transmission pipeline. It manages the simultaneous write and read operations on the same DDR space, coordinating the flow of data to ensure continuous operation without conflicts, thus reducing overall operation time while maintaining large storage capacity.
3Reliability
If separate caching and reading operations are performed sequentially, then data storage reliability is improved, but bandwidth utilization decreases and operation time increases
Solution Approach 1:
The unified FIFO operation enables continuous simultaneous write and read operations on the DDR memory through the same interface. Data flows continuously from ingress FIFO through DDR to egress FIFO without sequential pauses, maximizing bandwidth utilization while maintaining reliability through the robust FIFO control mechanism that coordinates both operations.
Data Source
AI summary
The present invention relates to a system for implementing large-scale FIFO data processing based on DDR, comprises ingress asynchronous clock domain FIFO; burst read and write data block chain table, for writing data block chaining table and reading data block chaining table by setting of data bit width and data block length; DDR4 AXI interface for interacting with the flow control state machine and the burst read and write chain table; egress asynchronous clock domain FIFO; flow control state machine, used for data flow control to monitor writes and reads of data streams to the ingress asynchronous clock domain FIFO, DDR4 AXI interface and egress asynchronous clock domain FIFO. The present invention also relates to a method for implementing DDR-based large-scale FIFO data processing using DDR. By adopting the system, method, device, processor and its computer-readable storage medium for implementing large-scale FIFO data processing based on DDR of the present invention, the time utilization rate is improved, the data acquisition efficiency is effectively improved, and the FIFO storage depth is increased to ensure continuous data acquisition for a longer period of time.