DDR Interface Frequency Adjustment via Spread Spectrum Clocking
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Solution Overview
Problem
Current DDR frequency adjustment methods require suspending access to the DDR memory during frequency switching, leading to increased cache requirements and performance issues for CPUs and service processors.
Innovation Solution
A System-On-a-Chip (SoC) with a spread spectrum clocking generator and a frequency adjustment module that allows gradual frequency adjustments of the DDR interface while maintaining access to the DDR memory, ensuring system performance by using a predetermined adjustment amount and interval within locking-in frequency and time ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional DDR frequency adjustment method is used, then frequency switching can be achieved, but access to DDR memory must be suspended during switching
Solution Approach 1:
The patent applies dynamics by transitioning from a static frequency switching approach to a dynamic gradual frequency adjustment approach. The frequency is adjusted step-by-step within the locking-in range rather than switching abruptly, allowing the system to adapt frequency while maintaining continuous memory access operations.
Solution Approach 2:
The patent implements continuity of useful action by ensuring that memory access operations continue without interruption during frequency adjustment. The gradual adjustment within the locking-in range maintains the phase-locked state, so the useful action of data reading/writing remains continuous throughout the frequency transition process.
2Adaptability or versatility
If frequency adjustment suspends memory access, then frequency can be changed, but cache capacity requirements increase
Solution Approach 1:
By maintaining continuous memory access during frequency adjustment through gradual step-by-step changes within the locking-in range, the patent eliminates the need for large cache buffers to store suspended operations. The useful action continues without interruption, so cache capacity requirements are reduced.
3Adaptability or versatility
If frequency adjustment suspends memory access, then frequency can be changed, but CPU and service processor performance deteriorate
Solution Approach 1:
The patent applies dynamics by using gradual frequency adjustment within the locking-in range rather than abrupt switching. This dynamic approach maintains memory access continuity, ensuring that CPU and service processor operations continue without suspension, thereby preserving system processing performance during frequency transitions.
4Reliability
If gradual frequency adjustment is used, then memory access continuity is maintained, but adjustment time increases
Solution Approach 1:
The patent applies partial action by adjusting frequency in small steps within the locking-in range rather than making large abrupt changes. This partial adjustment approach maintains memory access continuity while the adjustment duration is kept minimal by using efficient step-size control and leveraging the existing locking-in mechanism.
Data Source
AI summary
A frequency adjustment method, a System-On-a-Chip, and a terminal are provided. In the embodiments of this application, when an access bandwidth requirement on a DDR memory changes, a first frequency adjustment request for a DDR interface is generated using a CPU, and a working frequency of the DDR interface is adjusted. Because during adjustment of the working frequency of the DDR interface, the working frequency of the DDR interface is gradually adjusted according to a predetermined adjustment amount by which a frequency adjustment coefficient of a spread spectrum clocking generator is adjusted each time and a predetermined interval between two adjacent adjustments, it is ensured that a DLL in the DDR interface and a phase-locked loop in the spread spectrum clocking generator are in locking-in states, so that the DDR memory can still be accessed during frequency adjustment of the DDR interface and system performance is ensured.