DDR Input Latch Circuit for Timing Margin and False Latch Prevention
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in achieving high-speed data access efficiency due to limitations in interface rates, particularly with single-data rate (SDR) interfaces, which hinder the effective latching of input signals at high speeds required for double-data rate (DDR) interfaces in NAND-cell type flash memory devices.
Innovation Solution
The input circuit employs a configuration with first to third differential amplifier circuits and a data latch circuit, utilizing differential amplification and inverter circuits to detect input and strobe signals, generating output signals with adjusted phases to ensure accurate latching despite variations in slew rates, thereby enhancing timing margins and preventing false data latch operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the interface rate is increased to achieve higher data access efficiency, then productivity is improved, but the reliability of data latching deteriorates due to slew rate variations causing false latch operations
Solution Approach 1:
The patent changes the timing parameter by which the second latch circuit is controlled to latch the input signal. Specifically, the second latch circuit is controlled to latch the input signal at a timing different from when the first latch circuit is controlled, allowing the circuit to accommodate higher data rates while maintaining reliable latching by adjusting the temporal parameters of the latching operation
Solution Approach 2:
The patent divides the latching function into two separate latch circuits (first latch circuit and second latch circuit) that operate at different timings. This segmentation allows the system to handle high-speed data transfer by distributing the latching operations across multiple circuits with staggered timing, thereby maintaining reliability while achieving higher productivity
2Productivity
If the interface operates at higher speeds to improve productivity, then data transfer rate is increased, but false data latch operations occur due to timing margins being reduced
Solution Approach 1:
The patent applies preliminary action by controlling the first latch circuit to latch the input signal in advance before the strobe signal transitions. This advance latching ensures that data is captured at an optimal timing point that provides sufficient timing margin even at higher data transfer rates, preventing false latch operations while maintaining high productivity
Solution Approach 2:
The patent introduces dynamic timing control where the second latch circuit is controlled to latch the input signal at a timing that is adjusted based on the operating conditions. This dynamic adjustment of latching timing allows the circuit to adapt to higher data rates while maintaining adequate timing margins, thus increasing data transfer rate without sacrificing reliability
Data Source
AI summary
The first input circuit detects an input signal to output a first output signal having the same phase as the input signal. The second input circuit is configured to detect a first strobe signal to output a second output signal. The third input circuit is configured to detect a second strobe signal as a reversed signal of the first strobe signal to output a third output signal. A data latch circuit includes a first latch circuit and a second latch circuit. It is configured to latch the first output signal in either one of the first latch circuit or the second latch circuit according to the first output signal, the second output signal and the third output signal. It also allows the other one of the first latch circuit or the second latch circuit to input the first output signal thereto.