DDR Memory Interface Timing with Extendable PLL-DLL Architecture
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Solution Overview
Problem
Designing memory interface circuitry for double data rate (DDR) memories is challenging due to the need to process data at double the clock rate, manage bidirectional data strobe signals with specific timing, and adhere to tight timing restrictions, which are often difficult to achieve and require complex analysis and skilled personnel, and existing designs are not easily extendable for use with additional memories.
Innovation Solution
The solution involves an integrated circuit with a phase-locked loop (PLL) and delay-locked loops (DLLs) for generating and synchronizing clock signals, along with metal programmable components for adaptability, and a power regulation scheme to ensure accurate timing and phase offsetting, allowing for extendible clock distribution and data rate conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional clock distribution schemes are used, then circuit design is simpler, but timing precision and skew control deteriorate
Solution Approach 1:
The system divides the integrated circuit into multiple regions, each with its own local DLL and delay chain. This segmentation allows independent timing adjustment in each region while maintaining overall system synchronization, resolving the contradiction between timing precision and circuit complexity.
Solution Approach 2:
Delay elements are pre-configured with specific delay values during circuit design and fabrication. This preliminary action enables precise timing control to be achieved without complex real-time adjustment mechanisms, maintaining both timing precision and circuit simplicity.
2Adaptability or versatility
If multiple power supply domains are provided, then circuit functionality is improved, but voltage gradients and timing issues worsen
Solution Approach 1:
Each power supply domain is equipped with its own local voltage regulator that provides power specifically tailored to the timing requirements of that region. This local quality approach ensures that voltage gradients do not affect timing stability across different power domains.
Solution Approach 2:
The system uses feedback mechanisms where timing performance is monitored and used to adjust power distribution and delay element configuration. This feedback loop compensates for voltage gradient effects and maintains timing stability despite multiple power supply domains.
3Manufacturing precision
If circuit design is optimized for specific timing budget, then timing precision is improved, but design extendability deteriorates
Solution Approach 1:
The delay chain architecture is designed with universal delay elements that can be configured for different timing requirements. The same basic circuit structure can serve multiple timing budgets and be extended to additional memory interfaces without requiring complete redesign, achieving both timing precision and extendability.
Solution Approach 2:
The system employs dynamically adjustable delay elements whose delay values can be modified based on operating conditions and timing requirements. This dynamic capability allows the circuit to maintain optimal timing performance across different applications and memory types while using a single extendable design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and adaptable memory interface circuitry that meets timing budgets effectively, simplifies design validation, and allows for extension to wider bus configurations without significant redesign, improving data transfer accuracy and reducing the need for complex analysis.
Implementation Method 1
a phase locked loop (PLL) configured to generate at least one clock signal based on a reference signal
Implementation Method 2
a delay locked loop (DLL) configured to receive a representation of the clock signal and determine a number of delay elements corresponding to a specified phase offset
Implementation Method 3
timing of clock signals provided to a port of the ASIC may be skewed by routing dependent propagation delay
Implementation Method 4
the DLL has associated voltage regulation circuitry, the associated voltage regulation circuitry of the DLL providing regulated voltage to the delay chain of the DLL
Data Source
AI summary
An extendible timing architecture for an integrated circuit is disclosed. The extendible timing architecture provides metal programmable components for use with different operational clock frequencies. In some embodiments the architecture utilizes master/slave DLLs with a double data rate memory circuit.