DDR Interface Vernier Delay Control for Timing Alignment
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Solution Overview
Problem
DDR SDRAM interfaces face timing violations due to non-unity mark-space ratios in data transfer, leading to potential set-up and hold time errors, especially at higher clock frequencies, caused by variations in memory chip specifications and printed circuit board delays.
Innovation Solution
A double data rate interface with a delay locked loop that includes a Vernier delay mechanism using a ring oscillator with variable delay elements, allowing for precise control of the delay period by programming dividers to match the set-up time and data bus rise time, and compensating for additional delays through a buffer, ensuring optimal timing signals for data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fixed delay locked loop with 90° and 270° phase delays is used, then optimal timing is achieved for unity mark-space ratio, but timing violations occur when mark-space ratio deviates from unity
Solution Approach 1:
The patent implements a delay locked loop with dynamically adjustable delay elements that can be programmed to provide different delay values based on the actual mark-space ratio. Instead of fixed 90° and 270° delays, the system adjusts the delay periods adaptively to maintain optimal timing alignment between data strobe signal and latch signals regardless of mark-space ratio variations.
Solution Approach 2:
The patent changes the delay parameters of the locked loop by introducing programmable delay elements with adjustable delay periods. The system measures or detects the actual mark-space ratio and accordingly adjusts the delay values to compensate for deviations from unity ratio, thereby maintaining timing precision under varying conditions.
2Productivity
If clock frequency is increased to improve data transfer rate, then productivity increases, but timing violations and reliability decrease
Solution Approach 1:
The patent employs a dynamically adjustable delay locked loop that can adapt its delay characteristics to maintain timing compliance at higher clock frequencies. The programmable delay elements allow the system to optimize timing margins dynamically, ensuring reliable data latching even as operating frequency increases and timing margins become tighter.
3Ease of manufacture
If delay locked loop uses fixed quarter-period delays, then implementation is simple, but it cannot compensate for variations in memory chip specifications and PCB delays
Solution Approach 1:
The patent introduces programmable delay elements with adjustable delay periods that can be configured to compensate for process variations, memory chip specification differences, and PCB delay variations. The system allows for parameter adjustment of the delay locked loop to match actual system characteristics, thereby achieving both manufacturability and timing precision.
Data Source
AI summary
The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.