DDR JTAG TAP Controller Interface Design
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Solution Overview
Problem
Existing reduced pin JTAG interfaces face a reduction in communication bandwidth between a JTAG controller and device, limiting their effectiveness for device test, debug, and programming operations.
Innovation Solution
A high-speed, reduced pin JTAG interface utilizing double data rate (DDR) circuitry, which combines TDI and TMS signals into a single serialized signal, allowing for high-speed data transfer with reduced pin count by inputting and outputting data components on alternating clock edges, thereby maintaining communication bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If reduced pin JTAG interfaces are used, then the number of pins required is reduced, but the communication bandwidth between JTAG controller and device is reduced
Solution Approach 1:
The patent combines multiple JTAG signals (TDI, TMS, TDO) into a single bidirectional pin, reducing the number of pins required while maintaining communication functionality through time-division multiplexing and double data rate encoding
Solution Approach 2:
The patent employs double data rate (DDR) encoding where data is transmitted on both rising and falling edges of the clock signal, effectively doubling the communication bandwidth and compensating for the reduced pin count by increasing the data rate
2Adaptability or versatility
If reduced pin JTAG interfaces are used, then device pin availability is improved, but communication speed is reduced
Solution Approach 1:
The patent changes the timing parameters of signal transmission by utilizing both rising and falling edges of the clock cycle, effectively doubling the communication speed and compensating for the constraints of reduced pin availability
Data Source
AI summary
A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.