DDR Output Level Shift Circuit Layout to Eliminate Data Skew
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Solution Overview
Problem
In semiconductor devices, particularly DDR SDRAMs, level shifting internal clock and data signals to match external voltage amplitudes introduces signal skew due to differing delay times for rising and falling edges, degrading output data quality and limiting power consumption reduction.
Innovation Solution
Implementing a DLL circuit that generates internal clock signals with a single phase, which are then level-shifted and divided into complementary select clock signals, allowing for synchronized data output without skew, while maintaining internal voltage operation for most circuits to minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If level shift circuit is inserted in data path to convert internal voltage amplitude to external voltage amplitude, then data signal voltage level matches external requirement, but power consumption increases and signal skew occurs
Solution Approach 1:
The level shift circuit is positioned to perform level shifting at the final stage before data output, after the DLL circuit has completed its operations. This preliminary action at the optimal point allows internal circuits to operate at lower voltage while only the output stage converts to external voltage level, minimizing the number of high-voltage circuits and reducing overall power consumption.
Solution Approach 2:
The level shift circuit acts as an intermediary component that bridges the internal low-voltage domain and external high-voltage domain. By placing it at the output stage, it mediates the voltage level transition only where necessary for external communication, while allowing internal circuits to remain in the low-voltage domain for power efficiency.
2Use of energy by moving object
If level shift is performed within output circuit for DDR SDRAM, then power consumption is minimized, but skew occurs between rising edge and falling edge synchronized data
Solution Approach 1:
The clock signal path is segmented into separate rising edge path and falling edge path, with independent level shift circuits for each edge. This segmentation allows separate control and compensation of delay times for each edge, eliminating the skew that would occur if a single level shift circuit handled both edges.
Solution Approach 2:
Different delay compensation values are applied locally to the rising edge path and falling edge path based on their respective delay characteristics. The level shift circuits are designed with adjustable delay elements that can be independently tuned for each edge type, providing local optimization of signal timing.
3Ease of operation
If level shift circuit is placed early in the circuit path, then all subsequent circuits must operate at external voltage, but this increases power consumption
Solution Approach 1:
The level shifting action is delayed until the final necessary point in the signal path, after the DLL circuit has completed all its internal operations. This preliminary action at the optimal location allows maximum portion of the circuit to operate at lower internal voltage, reducing power consumption while still achieving the required external voltage level for output.
Data Source
AI summary
To include a first level shift circuit that converts a first internal clock signal having an amplitude value of a first voltage into a second internal clock signal having an amplitude value of a second voltage, a second level shift circuit that converts a first internal data signal having the amplitude value of the first voltage into a second internal data signal having the amplitude value of the second voltage, a clock dividing circuit that generates third and fourth internal clock signals, which are complementary signals, based on the second internal clock signal, and an output circuit that outputs external data signals continuously from a data output terminal in synchronization with the third and fourth internal clock signals based on the second internal data signal. According to the present invention, because a level shift of a signal is performed before it is input to the output circuit, there occurs no skew in output data.