DDR Memory Bus ODT Configuration for Reduced Preamble Time

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Solution Overview

Problem

Higher fundamental clock frequencies in DDR memory buses are prone to signal distortion due to signal reflections from improperly terminated signal lines, and existing ODT circuitry settings require time-consuming changes, affecting throughput.

Innovation Solution

Implementing separate and non-changing ODT configuration settings for DQS and /DQS signal traces, allowing them to maintain consistent values even during changes in memory bus operations, thereby reducing preamble time and maintaining optimal signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If higher fundamental clock frequencies are used in DDR memory bus, then data transfer speed is improved, but signal distortion increases due to signal reflections

Engineering Contradiction:

Improvedata transfer speedVSAvoidsignal integrity

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent changes the termination resistance parameter dynamically based on operating conditions. By adjusting the termination resistance value according to the fundamental clock frequency and signal characteristics, the system optimizes signal integrity at higher frequencies while maintaining compatibility with standard memory devices. This parameter adjustment reduces signal reflections and distortion without requiring changes to the memory device itself.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If ODT circuitry settings are changed to optimize signal termination, then signal integrity is improved, but preamble time increases due to configuration changes

Engineering Contradiction:

Improvesignal integrityVSAvoidpreamble time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary configuration of the ODT circuitry during initialization or idle periods, before actual data transfer operations begin. By pre-setting the termination resistance values based on the operating mode and frequency, the system avoids time-consuming configuration changes during active data transfers, thus reducing preamble time while maintaining optimal signal integrity.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamic ODT configuration that can adapt to different operating conditions without requiring full reconfiguration during data transfers. The system monitors signal quality and operating parameters, making real-time adjustments to termination resistance values to maintain optimal signal integrity while minimizing disruption to data transfer operations and reducing preamble overhead.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11074959B2DDR memory bus with a reduced data strobe signal preamble timespan

Publication Date: 2021.07.27 INTEL CORP

AI summary

A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.