DDR Memory Data Scrambling for Power Supply Noise Suppression
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Solution Overview
Problem
Double data rate memory systems face challenges in meeting tight jitter and timing specifications due to increasing IO frequencies, primarily attributed to power supply noise issues like package resonance and first droop, which are exacerbated by data patterns.
Innovation Solution
The implementation of data scrambling using parallel linear feedback shift registers (LFSRs) to generate pseudo-random outputs that are uncorrelated and XOR'd with data transmissions, resulting in a substantially white frequency spectrum, thereby reducing power supply noise on memory interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transmitted at higher IO frequencies to improve memory system performance, then productivity increases, but power supply noise increases causing jitter and timing errors
Solution Approach 1:
The patent applies parameter changes by transforming the data pattern parameters from deterministic to pseudo-random sequences. This changes the frequency spectrum characteristics of the transmitted signal, distributing energy more uniformly across frequencies rather than concentrating it at specific frequencies that resonate with power supply noise, thereby reducing the harmful effects of power supply noise while maintaining high IO frequencies
Solution Approach 2:
The patent converts the harmful effect of data patterns that cause resonance into a beneficial pseudo-random pattern that suppresses power supply noise. By using scramblers to generate pseudo-random sequences, the previously harmful concentrated frequency energy is transformed into a beneficial white noise-like spectrum that actually helps mask and suppress power supply noise, turning the data transmission itself into a noise-suppression mechanism
2Object-affected harmful factors
If data scrambling is applied to suppress power supply noise, then power supply noise is reduced, but device complexity increases due to additional scrambling logic
Solution Approach 1:
The patent uses copying by implementing identical scrambler and unscrambler logic at both transmitter and receiver ends. The scrambler creates a pseudo-random copy of the data pattern that is XORed with the original data, and the unscrambler at the receiving end uses the same logic to regenerate the pseudo-random sequence and remove it from the received signal. This copying approach suppresses power supply noise while maintaining system simplicity through symmetry
Solution Approach 2:
The scrambling logic serves multiple functions: it suppresses power supply noise by transforming data patterns, it provides data encryption/security, and it enables better clock recovery at the receiver. By making the scrambling logic multi-functional, the patent reduces the need for separate dedicated noise suppression circuits, thereby limiting the increase in device complexity while achieving noise suppression
Data Source
AI summary
Embodiments of the invention are generally directed to systems, methods, and apparatuses for suppressing power supply noise using data scrambling in double data rate memory systems. In some embodiments, an integrated circuit includes a transmit data path to transmit data to one or more memory devices. The transmit data path may include scrambling logic to generate, in parallel, N pseudo random outputs that are uncorrelated with each other. The output data and the pseudo random outputs are input to XOR logic. The transmit data path transmits the output the of XOR logic which has a substantially white frequency spectrum. Other embodiments are described and claimed.