DDR Memory Data Selection Circuit Reduces Wire Routing Complexity
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Solution Overview
Problem
Double data rate memory devices require extensive and complex wire routing due to multiple data paths for transferring data during read and write operations, necessitating a reduction in the number of data lines to simplify data communication.
Innovation Solution
A double data rate memory device with a data selection circuit that combines even and odd data into a single data line using sense amplifiers and a data processing circuit, allowing data transfer on two data paths controlled by a clock signal and the least significant bit of a column address.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple data paths are used for transferring data during read and write operations, then data transfer capability is improved, but wire routing complexity increases
Solution Approach 1:
The patent merges even data and odd data onto a single data line using a data selection circuit that multiplexes the data paths. The data selection circuit receives even data from a first sense amplifier and odd data from a second sense amplifier, then combines them on a single data line controlled by the least significant bit of the column address, thereby reducing wire routing complexity while maintaining data transfer capability
Solution Approach 2:
The single data line serves multiple functions by carrying both even and odd data through the data selection circuit. The data selection circuit acts as a universal interface that can transfer different data types (even/odd) depending on the control signal from the column address LSB, eliminating the need for separate dedicated data lines for each data path
2Productivity
If multiple data paths are used for transferring data, then data transfer efficiency is improved, but the number of data lines increases
Solution Approach 1:
The patent combines even data and odd data onto a single data line, reducing the total number of data lines from multiple separate lines to one shared data line. The data selection circuit enables this consolidation by multiplexing the data paths based on the least significant bit of the column address, maintaining data transfer efficiency while reducing the quantity of data lines
Data Source
AI summary
A double data rate memory device comprises first and second sense amplifiers, a data selection circuit, and a data processing circuit. The first sense amplifier is configured to provide even data loaded on a first input and output data line, and the second sense amplifier is configured to provide odd data loaded on a second input and output data line. The data selection circuit is connected to the first and second sense amplifiers and is configured to provide output data loaded on a single data line, and the data processing circuit connected to the data selection circuit and configured to transfer the even data and the odd data in first and second data paths. The even data and the odd data are combined into the output data of the data selection circuit, and the data selection circuit selects the output data in response to a least significant bit of a column address and transfers the selected data on the single data line in response to a clock signal.